AD9850

–8–

REV. H

DATA

BUS

LOW-PASS

FILTER

GND

PROCESSOR

XTAL

OSC

CLK

IOUTB

VINN

VINP

QOUT

QOUTB

IOUT

100k

100k

200

100

470pF

200

COMP

TRUE

CMOS

CLOCK

OUTPUTS

RSET

AD9850

5-POLE ELLIPTICAL

42MHz LOW-PASS

200

IMPEDANCE

8-b

5 PARALLEL DATA,

OR 1-b

40 SERIAL DATA,

RESET, AND 2

CLOCK LINES

Figure 1. Basic AD9850 Clock Generator Application

with Low-Pass Filter

VCA

Rx

IF IN

ADC ENCODE

I/Q MIXER

AND

LOW-PASS

FILTER

I

Q

8

8

AD9059

DUAL 8-BIT

ADC

DIGITAL

DEMODULATOR

Rx

BASEBAND

DIGITAL

DATA

OUT

ADC CLOCK

FREQUENCY

LOCKED TO Tx CHIP/

SYMBOL PN RATE

AD9850

CLOCK

GENERATOR

32

CHIP/SYMBOL/PN

RATE DATA

125MHz

REFERENCE

CLOCK

AGC

Figure 2. AD9850 Clock Generator Application in a

Spread-Spectrum Receiver

THEORY OF OPERATION AND APPLICATION

The AD9850 uses direct digital synthesis (DDS) technology, in the

form of a numerically controlled oscillator, to generate a frequency/

phase-agile sine wave. The digital sine wave is converted to analog

form via an internal 10-bit high speed D/A converter, and an

on-board high speed comparator is provided to translate the analog

sine wave into a low jitter TTL/CMOS compatible output square

wave. DDS technology is an innovative circuit architecture that

allows fast and precise manipulation of its output frequency under

full digital control. DDS also enables very high resolution in the

incremental selection of output frequency; the AD9850 allows an

output frequency resolution of 0.0291 Hz with a 125 MHz refer-

ence clock applied. The AD9850’s output waveform is phase con-

tinuous when changed.

The basic functional block diagram and signal flow of the

AD9850 configured as a clock generator is shown in Figure 4.

The DDS circuitry is basically a digital frequency divider function

whose incremental resolution is determined by the frequency of

the reference clock divided by the 2

tuning word. The phase accumulator is a variable-modulus

counter that increments the number stored in it each time it

receives a clock pulse. When the counter overflows, it wraps

around, making the phase accumulator’s output contiguous.

The frequency tuning word sets the modulus of the counter,

which effectively determines the size of the increment (

∆ Phase)

that is added to the value in the phase accumulator on the next

clock pulse. The larger the added increment, the faster the

accumulator overflows, which results in a higher output fre-

quency. The AD9850 uses an innovative and proprietary

algorithm that mathematically converts the 14-bit truncated

value of the phase accumulator to the appropriate COS value.

This unique algorithm uses a much reduced ROM look-up table

and DSP techniques to perform this function, which contributes

to the small size and low power dissipation of the AD9850. The

relationship of the output frequency, reference clock, and tuning

word of the AD9850 is determined by the formula

where:

∆ Phase is the value of the 32-bit tuning word.

CLKIN is the input reference clock frequency in MHz.

The digital sine wave output of the DDS block drives the inter-

nal high speed 10-bit D/A converter that reconstructs the sine

wave in analog form. This DAC has been optimized for dynamic

performance and low glitch energy as manifested in the low

jitter performance of the AD9850. Because the output of the

IF

FREQUENCY

IN

TUNING

WORD

AD9850

COMPLETE DDS

125MHz

REFERENCE

FILTER

RF

FREQUENCY

OUT

FILTER

3a. Frequency/Phase–Agile Local Oscillator

TUNING

WORD

AD9850

COMPLETE

DDS

125MHz

REFERENCE

CLOCK

FILTER

RF

FREQUENCY

OUT

PHASE

COMPARATOR

LOOP

FILTER

VCO

DIVIDE-BY-N

3b. Frequency/Phase–Agile Reference for PLL

TUNING WORD

REF

FREQUENCY

RF

FREQUENCY

OUT

PHASE

COMPARATOR

LOOP

FILTER

VCO

FILTER

PROGRAMMABLE

DIVIDE-BY-N

FUNCTION

AD9850

COMPLETE

DDS

3c. Digitally-Programmable Divide-by-N Function in PLL

Figure 3. AD9850 Complete DDS Synthesizer in

Frequency Up-Conversion Applications