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ADS8401 数据表(PDF) 12 Page - Texas Instruments |
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ADS8401 数据表(HTML) 12 Page - Texas Instruments |
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12 / 29 page ![]() www.ti.com †Signal internal to device CONVST BUSY CS = 0 CONVERT† SAMPLING† (When CS Toggle) BYTE RD = 0 tw1 tpd1 tpd2 tw4 tw2 tw3 tCONV tACQ tCONV Invalid DB[15:8] DB[7:0] MSB LSB td3 Previous Previous tcycle tsu(AB) tsu(AB) (used in normal conversion) CONVST (used in ABORT) tsu5 tpd2 th1 th1 tpd1 td3 td3 th4 LSB Previous td5 Invalid MSB MSB MSB MSB Invalid Invalid LSB th4 td5 tsu5 LSB Valid Hi−Z ten tdis ten td3 tdis Valid Valid Hi−Z Hi−Z CS RD BYTE DB[15:0] tsu4 ADS8406 SLAS426A – AUGUST 2004 – REVISED DECEMBER 2004 TIMING DIAGRAMS (continued) Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND—Auto Read Figure 5. Detailed Timing for Read Cycles 12 |
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