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RESET

POWER-ON INITIALIZATION

LAYOUT

ADS8406

SLAS426A – AUGUST 2004 – REVISED DECEMBER 2004

RESET is an asynchronous active low input signal (that works independently of CS). Minimum RESET low time

is 25 ns. Current conversion will be aborted no later than 50 ns after the converter is in the reset mode. In

addition, all output latches are cleared (set to zero's) after RESET. The converter goes back to normal operation

mode no later than 20 ns after RESET input is brought high.

The converter starts the first sampling period 20 ns after the rising edge of RESET. Any sampling period except

for the one immediately after a RESET is started with the falling edge of the previous BUSY signal or the falling

edge of CS, whichever is later.

Another way to reset the device is through the use of the combination of CS and CONVST. This is useful when

the dedicated RESET pin is tied to the system reset but there is a need to abort only the conversion in a specific

converter. Since the BUSY signal is held high during the conversion, either one of these conditions triggers an

internal self-clear reset to the converter just the same as a reset via the dedicated RESET pin. The reset does

not have to be cleared as for the dedicated RESET pin. A reset can be started with either of the two following

steps.

•

Issue a CONVST when CS is low and a conversion is in progress. The falling edge of CONVST must satisfy

a reset. The falling edge of CONVST starts a reset. Timing is the same as a reset using the dedicated

RESET pin except the instance of the falling edge is replaced by the falling edge of CONVST.

•

Issue a CS while a conversion is in progress. The falling edge of CS must satisfy the timing as specified by

CS causes a reset. Timing is the same as a reset using the dedicated RESET pin except the instance of the

falling edge is replaced by the falling edge of CS.

RESET is not required after power on. An internal power-on-reset circuit generates the reset. To ensure that all

of the registers are cleared, the three conversion cycles must be given to the converter after power on.

For optimum performance, care should be taken with the physical layout of the ADS8406 circuitry.

As the ADS8406 offers single-supply operation, it is often used in close proximity with digital logic,

microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and

the higher the switching speed, the more difficult it is to achieve good performance from the converter.

The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground

connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving

any single conversion for an n-bit SAR converter, there are at least n windows in which large external transient

voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby

digital logic, or high power devices.

The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the

external event.

On average, the ADS8406 draws very little current from an external reference, as the reference voltage is

internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive

the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor and a 1-µF storage capacitor

are recommended from pin 1 (REFIN) directly to pin 48 (REFM). REFM and AGND should be shorted on the

same ground plane under the device.

The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the

analog ground. Avoid connections which are close to the grounding point of a microcontroller or digital signal

processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal

layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.

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