Block diagram and pins description

L9823

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DocID7791 Rev 7

Table 2. Pins description

N#

Pin

Description

1

OUT7

Output 7

2

OUT6

Output 6

3SCLK

The system clock pin (SCLK) clocks the internal shift registers of the L9823. The serial input

pin (SI) accepts data into the input shift register on the falling edge of the SCLK signal while

the serial output pin (SO) shifts data information out of the shift register on the rising edge of

the SCLK signal. False clocking of the shift register must be avoided to guarantee validity of

data. It is essential that the SCLK pin be in a logic low state whenever chip select bar pin

(CSB) makes any transition. For this reason, it is recommended though not necessary, that

the SCLK pin be kept in a low logic state as long as the device is not accessed (CSB in logic

high state). When CSB is in a logic high state, any signal at the SCLK and SI pin is ignored

and SO is tri-stated (high-impedance).

4SI

This pin is for the input of serial instruction data. SI information is read in on the falling edge of

SCLK. A logic high state present on this pin when the SCLK signal rises will program a

specific output OFF, and in turn, turns OFF the specific output on the rising edge of the CSB

signal. Conversely, a logic low state present on the SI pin will program the output ON, and in

turn, turns ON the specific output on the rising edge of the CSB signal. To program the eight

outputs of the L9823 ON or OFF, an eight bit serial stream of data is required to be entered

into the SI pin starting with Output 7, followed by Output 6, Output 5, etc., to Output 0. For

each rise of the SCLK signal, with CSB held in a logic low state, a databyte instruction (ON or

OFF) is loaded into the shift register per the databyte SI state. The shift register is full after

eight bits of information have been entered. To preserve data integrity, care should be taken to

not transition SI as SCLK transitions from a low-to-high logic state.

5GND

GND

6GND

GND

7GND

GND

8GND

GND

9SO

The serial output (SO) pin is the tri-stateable output from the shift register. The SO pin

remains in a high impedance state until the CSB pin goes to a logic low state. The SO data

reports the drain status, either high or low. The SO pin changes state on the rising edge of

SCLK and reads out on the falling edge of SCLK. When an output is OFF and not faulted, the

corresponding SO databyte is a high state. When SO an output is ON, and there is no fault,

the corresponding databyte on the SO pin will be a low logic state. The SI / SO shifting of data

follows a first-in-first-out protocol with both input and output words transferring the Most

Significant Bit (MSB) first. The SO pin is not affected by the status of the Reset pin.

10

CSB

The system MCU selects the L9823 to be communicated with through the use of the CSB pin.

Whenever the pin is in a logic low state, data can be transferred from the MCU to the L9823

and vise versa. Clocked-in data from the MCU is transferred from the L9823 shift register and

latched into the power outputs on the rising edge of the CSB signal. On the falling edge of the

CSB signal, drain status information is transferred from the power outputs and loaded into the

device's shift register. The CSB pin also controls the output driver of the serial output pin.

Whenever the CSB pin goes to a logic low state, the SO pin output driver is enabled allowing

information to be transferred from the L9823 to the MCU. To avoid any spurious data, it is

essential that the high-to-low transition of the CSB signal occur only when SCLK is in a logic

low state.

11

OUT5

Output 5

12

OUT4

Output 4

13

OUT3

Output 3