L9823 datasheet(10/19 Pages) STMICROELECTRONICS

10 / 19 page

Electrical specifications

L9823

10/19

DocID7791 Rev 7

COUT

Output capacitance

VOUT = 16 V; f = 1 MHz

300

Outputs short circuit protection

ISCB

Overcurrent shutoff threshold

SFPD = Low, VOUT  VDG

0.5

1.6

2.5

IOUT LIM Short circuit current limitation

0.5

1.6

2.5

tdly SCB Short circuit shutdown delay

SFPD = Low, VOUT  VDG

CSB = 50% to

IOUT  1/2 IOUT LIM

150

250

µs

Diagnostics

VDG

Diagnostic threshold voltage

0.5·VDD

0.55·VDD 0.6·VDD

IOUT OL

Open load detection sink

current

Vout = VDG

Output programmed OFF

100

µA

tdly SFPD Diagnostic detection filter time

SFPD = Low, VOUT  VDG

CSB = 50% to valid data at SO

150

250

µs

Outputs timing

tdon

Turn-on delay

CSB = 50% to RL = 50 

VOUT = 0.9 Vbat, Vbat = 16 V

µs

tdoff

Turn-off delay

CSB = 50% to RL = 50 

VOUT = 0.1·Vbat, Vbat = 16 V

µs

dVon/dt Turn-on voltage slew-rate

90% to 30% of Vbat;

RL = 50 ; Vbat = 16 V

0.7

2.1

3.5

V/µs

dVoff/dt Turn-off voltage slew-rate

30% to 90% of Vbat;

RL = 50 ; Vbat = 16 V

0.7

2.1

3.5

V/µs

dVoff

clamp/dt

Turn-off voltage clamp slew-

rate

30% to 80% of VOUT clamp

RL = 500 

0.7

2.1

5.5

V/µs

Serial diagnostic link (Load capacitor at SO = 200 pF)

fsclk

Clock frequency

50% duty cycle

MHz

tclh

Minimum time SCLK = HIGH

160

tcll

Minimum time SCLK = LOW

160

tpcld

Propagation delay

SCLK to data at SO valid

4.9 V

 VDD  5.1 V

100

tcsdv

CSB = LOW to data at SO

active

100

tsclch

SCLK low before CSB low

Setup time SCLK to CSB change

H/L

100

thclcl

SCLK change L/H after CSB =

Low

Setup time CSB to SCLK change

L/H

100

tscld

SI input setup time

SCLK change H/L after SI data

valid

Table 5. Electrical characteristics (continued)

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

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