REV. B

AD1555/AD1556

–18–

the other switches are opened, and a reference voltage (2.25 V)

equal to half of the full-scale range is sampled. In this combina-

tion, the gain setting is forced to be the gain of 1.

When the signal input is selected, S1(+) and S1(–) are closed, all

the other switches are opened, and the differential input signal

between AIN(+) and AIN(–) is sampled. This is the main path

for signal acquisition.

When the test input is selected, S2(+) and S2(–) are closed, all

the other switches are opened, and the differential input signal

between TIN(+) and TIN(–) is sampled. This combination

allows acquisition of a test signal or a secondary channel with

the same level of performance as with AIN inputs. By applying

known voltages to these inputs, it is also possible to calibrate the

gain for each gain setting.

When the Sensor Test 1 is selected, S1(+), S1(–), S2(+), and

S2(–) are closed, all the other switches are opened, and the gain

setting is forced to be the gain of 1. In this configuration, a

source between TIN(+) and TIN(–) may be applied to the

sensor to determine its impedance or other characteristics. The

total internal serial resistance between each AIN input and the

PGA inputs, nominally 66

Ω, slightly affects these measurements.

The total internal serial resistance between each TIN input and

the PGA inputs is nominally 116

Ω.

When the Sensor Test 2 is selected, S1(+), S2(+), and S2(–)

are closed, all the other switches are opened. This configuration

could be used to test the sensor isolation.

Power-Down Modes of the AD1555

The AD1555 has two power-down modes. The multiplexer and

programmable gain amplifier can be powered down by the

CB2–CB0 setting of “101.” The entire chip is powered down by

either CB2–CB1 set to “11” or by keeping the clock input MCLK

at a fixed level high or low. Less shutdown current flows with

MCLK low. The least power dissipation is achieved when the

external reference is shut down eliminating the current through

the 30 k

Ω nominal load at REFIN. When in power-down, the

multiplexer is switched to the “ground input.”

DAC

MDATA

LOOP FILTER

20k

COMPARATOR

INTEGRATOR

MODIN

Figure 9. Sigma-Delta Modulator Block Diagram

SIGMA-DELTA MODULATOR

The AD1555 sigma-delta modulator achieves its high level of

performance, notably in dynamic range and distortion, through

the use of a switched-capacitor feedback DAC in an otherwise

continuous-time design. Novel circuitry eliminates the subtle

distortion normally encountered when these disparate types are

connected together. As a result, the AD1555 enjoys many of the

benefits of both design techniques.

Because of the switched-capacitor feedback, this modulator is

much less sensitive to timing jitter than is the usual continuous-

time design that relies on the duty cycle of the clock to control a

switched-current feedback DAC.

Unlike its fully switched-capacitor counterparts, the modulator

input circuitry is nonsampling, consisting simply of an internal,

low temperature coefficient resistor connected to the summing

node of the input integrator. Among the advantages of this

continuous-time architecture is a relaxation of requirements for

the antialias filter; in fact, the output of the programmable gain

amplifier, PGAOUT, may be tied directly to the input of the

modulator MODIN without any external filter. Another advan-

tage is that the gain may be adjusted to accommodate a higher

input range by adding an external series resistor at MODIN.

The modulator of the AD1555 is fourth order, which very effi-

ciently shapes the quantization noise so that it is pushed toward

the higher frequencies (above 1 kHz) as shown in TPC 3. This

high frequency noise is attenuated by the AD1556 digital filter.

However, when the output word rate (OWR) of the AD1556 is

higher than 4 kHz (–3 dB frequency is higher than 1634 Hz),

the efficiency of this filtering is limited and slightly reduces the

dynamic range, as shown in the Table I. Hence, when possible,

an OWR of 2 kHz or lower is generally preferred.

Sigma-delta modulators have the potential to generate idle tones

that occur for dc inputs close to ground. To prevent this unde-

sirable effect, the AD1555 modulator offset is set to about –60 mV.

In this manner, any existing idle tones are moved out of the

band of interest and filtered out by the digital filter.

Also, sigma-delta modulators may oscillate when the analog

input is overranged. To avoid any instability, the modulator of

the AD1555 includes circuitry to detect a string of 16 identical

bits (“0” or “1”). Upon this event, the modulator is reset by

discharging the integrator and loop filter capacitors and MFLG

is forced high. After 1.5 MCLK cycles, MFLG returns low.