REV. B

AD1555/AD1556

–20–

RESET Operation

The RESET pin initializes the AD1556 in a known state.

RESET is active on the next CLKIN rising edge after the

RESET input is brought high as shown in Figure 4. The reset

value of each bit of the configuration and the status registers are

indicated in Table V and Table VIII. The filter memories are

not cleared by the reset. Filter convolutions begin on the next

CLKIN rising edge after the RESET input is returned low. A

RESET operation is done on power-up, independent of the

RESET pin state.

In multiple ADCs applications where absolute synchroniza-

tion—even below the noise floor—is required, RESETD, which

resets the decimator, can be tied to RESET to ensure this

synchronization.

Power-Down Operation

The PWRDN pin puts the AD1556 in a power-down state.

PWRDN is active on the next CLKIN rising edge after the

PWRDN input is brought high. While in this state, MCLK is

held at a fixed level and the AD1555 is therefore powered

down too. The serial interface remains active allowing read and

write operations of the AD1556. The configuration and status

registers maintain their content during the power-down state.

SYNC Operation

SYNC is used to create a relationship between the analog input

signal and the output samples of the AD1556. The SYNC event

does two things:

clock, CLKIN, as shown in Figure 3.

Exactly one sampling rate delay later, the DRDY pin goes

high. A SYNC event occurs on the next CLKIN rising edge

after the SYNC input is brought high as shown in Figure 3.

The DRDY output goes high on the next falling edge of

CLKIN. SYNC may be applied once or kept high, or applied

synchronously at the output word rate, all with the same effect.

Configuring and Interfacing the AD1556

The AD1556 configuration can be loaded either by hardware

(H/

S pin high) or via the serial interface of the AD1556 (H/S

pin low). To operate with the AD1556, the CLKIN clock must be

kept running at the nominal frequency of 1.024 MHz. Table V

gives the description of each bit of the configuration register and

Table VI defines the selection of the filter bandwidth. When the

software mode is selected (H/

S pin low), the configuration register

is loaded using the pins DIN, SCLK,

CS, and R/W. In this mode,

when RESET is active, the configuration register mimics the selec-

tion of the hardware pins. The AD1556 and the AD1555 can be

put in power-down by software.

The DRDYBUF bit controls the operating mode of the DRDY

output pin. When the DRDYBUF bit is low, the DRDY is a con-

ventional CMOS push-pull output buffer as shown in Figure 11.

When the DRDYBUF bit is high, the DRDY output pin is an

open drain PMOS pull-up as shown in Figure 11. Many DRDY

pins may be connected with an external pull-down resistor in a

wired OR to minimize the interconnection between the AD1556s

and the microprocessor in multichannel applications. The DRDY

pin is protected against bit contention.

By connecting DRDY to RSEL directly, and applying 48 SCLK

cycles, both data and status can be read sequentially, data

register first.

Table VI. Filter Bandwidth Selection

BW2

BW1

BW0

Output Rate (ms)

00

0

4

00

1

2

01

0

1

01

1

1/2

10

0

1/4

10

1

1/8

11

0

1/16

11

1Reserved

Table V. Configuration Register Data Bits

Bit

Number

Name

Description

RESET State

DB15 (MSB)

X

X

DB14

X

X

DB13

X

X

DB12

X

X

DB11

PWRDN

Power-Down Mode

PWRDN

DB10

CSEL

Select TDATA Input

CSEL

DB9

X

X

DB8

BW2

Filter Bandwidth Selection

BW2

DB7

BW1

Filter Bandwidth Selection

BW1

DB6

BW0

Filter Bandwidth Selection

BW0

DB5

DRDYBUF

DRDY Output Mode

0 (Push-Pull)

DB4

CB4

PGA Input Select

PGA4

DB3

CB3

PGA Input Select

PGA3

DB2

CB2

PGA Gain Select

PGA2

DB1

CB1

PGA Gain Select

PGA1

DB0 (LSB)

CB0

PGA Gain Select

PGA0