REV. B

AD1555/AD1556

–19–

DIGITAL FILTERING

The AD1556 is a digital finite impulse response (FIR) linear

phase low pass filter and serves as the decimation filter for the

AD1555. It takes the output bitstream of the AD1555, filters

and decimates it by a user-selectable choice of seven different

filters associated with seven decimation ratios, in power of 2

from 1/16 to 1/1024. With a nominal bit rate of 256 kbits/s at

the AD1556 input, the output word rate (the inverse of the

sampling rate) ranges from 16 kHz (1/16 ms) to 250 Hz (4 ms) in

powers of 2. The AD1556 filter achieves a maximum pass band

flatness of

±0.05 dB for each decimation ratio and an out-of-

band attenuation of –135 dB maximum for each decimation

ratio except 1/16 (OWR = 16 kHz) at which the out-of-band

attenuation is –86 dB maximum. Table II gives for each filter

the pass band frequency, the –3 dB frequency, the stop-band

frequency, and the group delay. The pass band frequency is 37.5%

of the output word rate, and the –3 dB frequency is approximately

41% of the output word rate. The noise generated by the AD1556,

even that due to the word truncation, has a negligible impact on

the dynamic range performance of the AD1555/AD1556 chipset.

Although dedicated to the AD1555, the AD1556 can also be

used as a very efficient and low power, low pass, digital filter of

a bitstream generated by other

-

modulators.

Architecture

The functional block diagram of the filter portion of the AD1556 is

given in Figure 10. The basic architecture is a two-stage filter.

The second stage has a decimation ratio of 4 for all filters except

at the output word rate of 250 Hz, where the decimation ratio is

8. Each filter is a linear phase equiripple FIR implemented by

summing symmetrical pairs of data samples and then convolut-

ing by multiplication and accumulation.

The input bitstream at 256 kHz enters the first filter and is

multiplied by the 26-bit wide coefficients tallied in Table IV.

Due to the symmetry of the filter, only half of the coefficients

are stored in the internal ROM and each is used twice per con-

volution. Because the multiplication uses a 1-bit input data, the

convolution for the first stage is implemented with a single accu-

mulator 29-bits wide to avoid any truncation in the accumulation

process. The output of the first-stage filter is decimated with the

ratios given in Table IV and then are stored in an internal RAM

which truncates the accumulator result to 24 bits.

The second-stage filter architecture is similar to the first stage.

The main difference is the use of a true multiplier. The multiplier,

the accumulator, and the output register, which are respectively

32-bits, 35-bits and 24-bits wide, introduce some truncation

that does not affect the overall dynamic performance of the

AD1555/AD1556 chipset.

Filter Coefficients

As indicated before, each stage for each filter uses a different

set of coefficients. These coefficients are provided with the

EVAL-AD1555/AD1556EB, the evaluation board for the

AD1555 and the AD1556.

Table IV. Filter Definition

Decimation Ratio

Number of Coefficients

(Sampling Rate [ms])

First Stage

Second Stage

First Stage

Second Stage

16000 [1/16 ms]

4

4

32

118

8000 [1/8 ms]

8

4

64

184

4000 [1/4 ms]

16

4

128

184

2000 [1/2 ms]

32

4

256

184

1000 [1 ms]

64

4

512

184

500 [2 ms]

128

4

1024

184

250 [4 ms]

128

8

1024

364

FIRST-STAGE FILTER

INPUT DATA STORAGE

MODULATOR BITSTREAM

1-BIT WIDE AT 256kbits/s

FIRST-STAGE

FILTER 29-BIT

ACCUMULATOR

MULTIPLIER

35-BIT

ACCUMULATOR

RAM 1024

BY 1 BIT

FIRST-STAGE

FILTER

COEFFICIENTS

ROM 1008 BY 26 BITS

RAM 364 BY 24 BITS

ROM 333 BY 26 BITS

SECOND-STAGE

FILTER INPUT

DATA STORAGE

SECOND-STAGE

FILTER INPUT

COEFFICIENTS

SECOND-STAGE FILTER

124

24

32

26

26

24

Figure 10. AD1556 Filter Functional Block Diagram