ADCLK914BCPZ-R2 datasheet(4/12 Pages) AD

部件名	ADCLK914BCPZ-R2

功能描述	Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer

PDF	12 Pages

Scroll/Zoom	100%

制造商	AD [Analog Devices]

网页	http://www.analog.com

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4 / 12 page

ADCLK914

Rev. A | Page 4 of 12

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

122.88 MHz

−150

dBc/Hz

@10 Hz offset

−156

dBc/Hz

@100 Hz offset

−160

dBc/Hz

@1 kHz offset

−161

dBc/Hz

@10 kHz offset

−161

dBc/Hz

@100 kHz offset

−160

dBc/Hz

>1 MHz offset

POWER SUPPLY

Supply Voltage Requirement

VCC

2.97

3.63

Power Supply Current

Negative Supply Current

IVEE

111

150

Includes output current

Positive Supply Current

IVCC

Power Supply Rejection2

PSRVCC

ps/V

VCC = 3.3 V ± 10%

Output Swing Supply Rejection3

−15

VCC = 3.3 V ± 10%

1 Calculated from SNR of ADC method. See Figure 8 for rms jitter vs. input slew rate.

2 Change in tPD per change in VCC.

3 Change in output swing per change in VCC.

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