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ADCLK914BCPZ-R2 数据表(PDF) 7 Page - Analog Devices

部件名 ADCLK914BCPZ-R2
功能描述  Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer
PDF  12 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADCLK914BCPZ-R2 数据表(HTML) 7 Page - Analog Devices

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ADCLK914
Rev. A | Page 7 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, VEE = 0 V, TA = 25°C. All outputs terminated through 50 Ω to VCC, unless otherwise noted.
Q
Q
62.5ps/DIV
Figure 3. Output Waveform at 1 GHz, VCC = 3.3 V
–120
–130
–140
–150
–160
–170
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 4. Phase Noise at 122.88 MHz
–120
–130
–140
–150
–160
–170
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 5. Phase Noise at 245.76 MHz
Q
Q
100ps/DIV
Figure 6. Output Waveform at 1 GHz, VCC = 3.3 V
–120
–130
–140
–150
–160
–170
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 7. Phase Noise at 622.08 MHz
350
0
0
1
234
56
78
INPUT SLEW RATE (V/ns)
300
250
200
150
100
50
TA = 25°C
Figure 8. RMS Jitter vs. Input Slew Rate



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