MPC8323E datasheet(33/82 Pages) FREESCALE

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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4

Freescale Semiconductor

11 I2C

This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8323E.

11.1

I2C DC Electrical Characteristics

Table 33 provides the DC electrical characteristics for the I2C interface of the MPC8323E.

11.2

I2C AC Electrical Specifications

Table 34 provides the AC timing parameters for the I2C interface of the MPC8323E.

Table 33. I2C DC Electrical Characteristics

At recommended operating conditions with OVDD of 3.3 V ± 10%.

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage level

VIH

0.7

× OVDD

OVDD + 0.3

—

Input low voltage level

VIL

–0.3

0.3

× OVDD

V—

Low level output voltage

VOL

00.4

Output fall time from VIH(min) to VIL(max) with a bus

capacitance from 10 to 400 pF

tI2KLKV

20 + 0.1

× CB

250

Pulse width of spikes which must be suppressed by the

input filter

tI2KHKL

050

Capacitance for each I/O pin

—10

—

Input current (0 V

≤ VIN ≤ OVDD)IIN

—±5

μA4

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. CB = capacitance of one bus line in pF.

3. Refer to the

MPC8323E PowerQUICC II Pro Integrated Communications Processor Reference Manual for information on the

digital filter used.

4. I/O pins obstructs the SDA and SCL lines if OVDD is switched off.

Table 34. I2C AC Electrical Specifications

All values refer to VIH (min) and VIL (max) levels (see Table 33).

Parameter

Symbol1

Min

Max

Unit

SCL clock frequency

fI2C

0400

kHz

Low period of the SCL clock

tI2CL

1.3

—

μs

High period of the SCL clock

tI2CH

0.6

—

μs

Setup time for a repeated START condition

tI2SVKH

0.6

—

μs

Hold time (repeated) START condition (after this period, the first clock

pulse is generated)

tI2SXKL

0.6

—

μs

Data setup time

tI2DVKH

100

—

Data hold time:

CBUS compatible masters

I2C bus devices

tI2DXKL

—

0.93

μs

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