MPC8323E datasheet(16/82 Pages) FREESCALE

部件名	MPC8323E

功能描述	PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications

PDF	82 Pages

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制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4

Freescale Semiconductor

DDR1 and DDR2 SDRAM

Figure 4 shows the input timing diagram for the DDR controller.

Figure 4. DDR Input Timing Diagram

6.2.2

DDR1 and DDR2 SDRAM Output AC Timing Specifications

Table 19 provides the output AC timing specifications for the DDR1 and DDR2 SDRAM interfaces.

Table 19. DDR1 and DDR2 SDRAM Output AC Timing Specifications

At recommended operating conditions with D

n_GVDD of (1.8 or 2.5 V) ± 5%.

Parameter

Symbol1

Min

Max

Unit

Notes

MCK cycle time, (MCK/MCK crossing)

tMCK

7.5

ADDR/CMD output setup with respect to MCK

tDDKHAS

266 MHz

200 MHz

2.5

3.5

—

ADDR/CMD output hold with respect to MCK

tDDKHAX

266 MHz

200 MHz

2.5

3.5

—

MCS output setup with respect to MCK

tDDKHCS

266 MHz

200 MHz

2.5

3.5

—

MCS output hold with respect to MCK

tDDKHCX

266 MHz

200 MHz

2.5

3.5

—

MCK to MDQS Skew

tDDKHMH

–0.6

0.6

MCK[n]

tMCK

MDQ[x]

MDQS[n]

tDISKEW

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