BQ76PL536APAPR datasheet(36/60 Pages) TI1

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bq76PL536A

SLUSAD3A – JUNE 2011 – REVISED AUGUST 2012

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DEVICE_STATUS REGISTER (0x00)

FAULT

ALERT

–

ECC_COR

UVLO

CBT

DRDY

The STATUS register provides information about the current state of the bq76PL536A.

[7]

This bit is written to indicate that the ADDR[0]…[5] bits have been written to the correct

(ADDR_RQST)

address. This bit is a copy of in the ADDRESS_CONTROL[AR] bit.

0 = Address has not been assigned

1 = Address has been assigned

[6] (FAULT):

This bit indicates that this bq76PL536A has detected a condition causing the FAULT signal

to become asserted.

0 = No FAULT exists

1 = A FAULT exists. Read FAULT_STATUS[] to determine the cause.

[5] (ALERT):

This bit indicates that this bq76PL536Av has detected a condition causing the ALERT pin to

become asserted.

0 = No FAULT exists

1 = An ALERT exists. Read ALERT_STATUS[] to determine the cause.

[4] (not implemented)

[3] (ECC_COR):

This bit indicates a one-bit error has been detected and corrected in the EPROM.

0 = No errors are detected in the EPROM

1 = A one-bit (single bit) error has been detected and corrected by on-chip logic.

[2] (UVLO):

This bit indicates the device VBAT has fallen below the undervoltage lockout trip point.

Some device operations are not valid in this condition.

0 = Normal operation

1 = UVLO trip point reached, device operation is not ensured.

[1] (CBT):

This bit indicates the cell balance timer is running.

0 = The cell balance timer is has not started or has expired.

1 = The cell balance timer is running.

[0] (DRDY):

This bit indicates the data is ready to read (no conversions active).

0 = There are conversion(s) running.

1 = There are no conversion(s) running.

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