VIPER37 datasheet(22/35 Pages) STMICROELECTRONICS

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Operation description

VIPER37

22/35

Doc ID 022218 Rev 1

Figure 26.

Timing diagram: soft-start

8.4

Power down operation

At converter power down, the system loses regulation as soon as the input voltage is so low

that the peak current limitation is reached. The VDD voltage drops and when it falls below

the VDDoff threshold (see Table 7) the Power MOSFET is switched OFF, the energy transfers

to the IC interrupted and consequently the VDD voltages decrease, Figure 25. Later, if the

VIN is lower than VDRAIN_START (see Table 7), the startup sequence is inhibited and the

power down completed. This feature is useful to prevent the converter’s restart attempts and

ensures monotonic output voltage decay during the system power down.

8.5

Auto-restart operation

If, after a converter power down, the VIN is higher than VDRAIN_START, the startup sequence

is not inhibited and is activated only when the VDD voltage drops below the VDD(RESTART)

threshold (see

Table 7). This means that the HV startup current generator restarts the VDD

capacitor charging only when the VDD voltage drops below VDD(RESTART). The scenario

described above is, for instance, a power down because of a fault condition. After a fault

condition, the charging current IDDch is 0.6 mA (typ.) instead of the 3 mA (typ.) of a normal

startup converter phase. This feature, together with the low VDD(RESTART) threshold,

ensures that, after a fault, the restart attempts of the IC have a very long repetition rate and

the converter works safely with extremely low power throughput.

Figure 27 shows the IC

behavior after a short-circuit event.

FBlin

FBolp

IDRAIN

V FB

tss

IDlim

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