VIPER37

Operation description

Doc ID 022218 Rev 1

27/35

capacitor may not be at its nominal value and the controller interprets this situation as an

overload condition. In this case, the OLP delay helps to avoid an incorrect device shutdown

during the startup phase.

Owing to the above considerations, the OLP delay time must be long enough to bypass the

initial output voltage transient and check the overload condition only when the output voltage

is in steady-state. The output transient time depends on the value of the output capacitor

and on the load.

ensure enough OLP delay, an alternative compensation network can be used, shown in

Figure 31.

pole is usually used to compensate the high frequency zero due to the ESR (equivalent

series resistor) of the output capacitance of the flyback converter.

The mathematical expressions of these poles and zero frequency, considering the scheme

in

Figure 31, are reported by the equations below:

Equation 6

Equation 7

Equation 8

cases, the loop stability and the correct OLP delay time alike.

1

FB

1

FB

ZFB

R

C

2

1

f

⋅

⋅

π

⋅

=

()

1

FB

)

DYN

(

FB

FB

1

FB

)

DYN

(

FB

PFB

R

R

C

2

R

R

f

⋅

⋅

⋅

π

⋅

+

=

()

)

DYN

(

FB

1

FB

1

FB

1

PFB

R

R

C

2

1

f

+

⋅

⋅

π

⋅

=