AD7440BRT-R2 datasheet(20/28 Pages) AD

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AD7440/AD7450A

Rev. C | Page 20 of 28

Example 1

Table 6. Examples of Suitable Voltage References

Output

Voltage (V)

Initial

Accuracy (%)

Operating

Current (μA)

VIN max = VDD + 0.3

VIN max = VREF + VREF/2

Reference

AD780

2.5/3

0.04

1000

If VDD = 5 V, then VIN max = 5.3 V.

Therefore

3 × VREF/2 = 5.3 V

VREF max = 3.5 V

Thus, when operating at VDD = 5 V, the value of VREF can range

from 100 mV to a maximum value of 3.5 V. When VDD = 4.75 V,

VREF max = 3.17 V.

Example 2

VIN max = VDD + 0.3

VIN max = VREF + VREF/2

If VDD = 3 V, then VIN max = 3.3 V.

Therefore,

3 × VREF/2 = 3.3 V

VREF max = 2.2 V

Thus, when operating at VDD = 3 V, the value of VREF can range

from 100 mV to a maximum value of 2.2 V. When VDD = 2.7 V,

VREF max = 2 V.

These examples show that the maximum reference applied to

the AD7440/AD7450A is directly dependent on the value

applied to VDD.

The value of the reference sets the analog input span and the

common-mode voltage range. Errors in the reference source

result in gain errors in the AD7440/AD7450A transfer function

and add to specified full-scale errors on the part. A 0.1 μF

capacitor should be used to decouple the VREF pin to GND.

Figure 38 shows a typical connection diagram for the VREF pin.

Table 6 lists examples of suitable voltage references.

AD780

VIN

GND

TEMP

OPSEL

TRIM

VOUT

AD7440/

AD7450A*

VREF

2.5V

VDD

NC = NO CONNECT

10nF

0.1

μF

0.1

μF

0.1

μF

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 38. Typical VREF Connection Diagram for VDD = 5 V

ADR421

2.5

0.04

500

ADR420

2.048

0.05

500

SINGLE-ENDED OPERATION

When supplied with a 5 V power supply, the AD7440/AD7450A

can handle a single-ended input. The design of these devices is

optimized for differential operation, so with a single-ended

input, performance degrades. Linearity degrades by typically

0.2 LSB, the full-scale errors degrade typically by 1 LSB, and ac

performance is not guaranteed.

To operate the AD7440/AD7450A in single-ended mode, the

input is coupled to the signal source, while the V

IN+

IN–

input is

biased to the appropriate voltage corresponding to the midscale

code transition. This voltage is the common mode, which is a

fixed dc voltage (usually the reference). The VIN+ input swings

around this value and should have a voltage span of 2 × VREF to

make use of the full dynamic range of the part. The input signal

therefore has peak-to-peak values of common mode ±VREF. If

the analog input is unipolar, an op amp in a noninverting unity

gain configuration can be used to drive the VIN+ pin. The ADC

operates from a single supply, so it is necessary to level shift

ground-based bipolar signals to comply with the input

requirements. An op amp can be configured to rescale and level

shift the ground-based bipolar signal, so it is compatible with

the selected input range of the AD7440/AD7450A (Figure 39).

2.5V

+2.5V

–2.5V

0.1

μF

AD7440/

AD7450A

VREF

VIN+

VIN–

VIN

EXTERNAL

VREF (2.5V)

Figure 39. Applying a Bipolar Single-Ended Input to the AD7440/AD7450A

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