AD7440BRT-R2 datasheet(25/28 Pages) AD

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AD7440/AD7450A

Rev. C | Page 25 of 28

Thus, the average power dissipated during each cycle with a

throughput rate of 100 kSPS is (2/10) × 4 mW = 0.8 mW.

The connection diagram is shown in Figure 45. The ADSP-21xx

has the TFS and RFS of the SPORT tied together, with TFS set

as an output and RFS set as an input. The DSP operates in

alternate framing mode and the SPORT control register is set

up as described. The frame synchronization signal generated on

the TFS is tied to

This is how the power numbers in Figure 44 are calculated.

For throughput rates above 320 kSPS, it is recommended to

reduce the serial clock frequency for best power performance.

CS and, as with all signal processing

applications, equidistant sampling is necessary. However in this

example, the timer interrupt is used to control the sampling rate

of the ADC; under certain conditions, equidistant sampling

may not be achieved.

THROUGHPUT (kSPS)

100

350

0.01

100

150

200

250

300

0.1

VDD = 5V

VDD = 3V

The timer registers, for example, are loaded with a value that

provides an interrupt at the required sample interval. When an

interrupt is received, a value is transmitted with TFS/DT (ADC

control word). The TFS is used to control the RFS and therefore

the reading of data. The frequency of the serial clock is set in

the SCLKDIV register. When the instruction to transmit with

TFS is given (AX0 = TX0), the state of the SCLK is checked.

The DSP waits until the SCLK has gone high, low, and high

again before starting transmission. If the timer and SCLK values

are chosen such that the instruction to transmit occurs on or

near the rising edge of SCLK, then the data may be transmitted

or it may wait until the next clock edge.

Figure 44. Power vs. Throughput Rate for Power-Down Mode

MICROPROCESSOR AND DSP INTERFACING

AD7440/

AD7450A*

ADSP-21xx*

SCLK

RFS

TFS

SCLK

SDATA

*ADDITIONAL PINS REMOVED FOR CLARITY

The serial interface on the AD7440/AD7450A allows the parts

to be directly connected to many different microprocessors.

This section explains how to interface the AD7440/AD7450A

with some of the more common microcontroller and DSP serial

interface protocols.

AD7440/AD7450A to ADSP-21xx

The ADSP-21xx family of DSPs is interfaced directly to the

AD7440/AD7450A without any glue logic required.

Figure 45. Interfacing to the ADSP-21xx

The SPORT control register should be set up as follows:

For example, the ADSP-2111 has a master clock frequency of

16 MHz. If the SCLKDIV register is loaded with the value 3, an

SCLK of 2 MHz is obtained and eight master clock periods

elapse for every SCLK period. If the timer registers are loaded

with the value 803, then 100.5 SCLKs occur between interrupts

and subsequently between transmit instructions. This situation

results in nonequidistant sampling as the transmit instruction is

occurring on a SCLK edge. If the number of SCLKs between

interrupts is a whole integer figure of N, equidistant sampling is

implemented by the DSP.

Table 7.

Parameter

Description

TFSW = RFSW = 1

Alternate framing

INVRFS = INVTFS = 1

Active low frame signal

DTYPE = 00

Right-justify data

SLEN = 1111

16-bit data-words

ISCLK = 1

Internal serial clock

TFSR = RFSR = 1

Frame every word

IRFS = 0

ITFS = 1

To implement power-down mode, SLEN should be set to 1001

to issue an 8-bit SCLK burst.

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