AD7440BRT-R2 datasheet(23/28 Pages) AD

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AD7440/AD7450A

Rev. C | Page 23 of 28

MODES OF OPERATION

POWER-DOWN MODE

The operational mode of the AD7440/AD7450A is selected by

controlling the logic state of the CS signal during a conversion.

There are two possible modes of operation, normal and power-

down. The point at which

This mode is intended for use in applications where slower

throughput rates are required; either the ADC is powered down

between each conversion, or a series of conversions may be

performed at a high throughput rate and the ADC is then

powered down for a relatively long duration between these

bursts of conversions. When the AD7440/AD7450A are in the

power-down mode, all analog circuitry is powered down. To

enter power-down mode, the conversion process must be

interrupted by bringing

CS is pulled high after the conversion

has been initiated determines whether or not the device enters

power-down mode. Similarly, if already in power-down, CS

controls whether the devices return to normal operation or

remain in power-down. These modes of operation are designed

to provide flexible power management options. These options

can be chosen to optimize the power dissipation/throughput

rate ratio for differing application requirements.

CS high anywhere after the second

falling edge of SCLK and before the 10th falling edge of SCLK,

as shown in Figure 42.

NORMAL MODE

This mode is intended for fastest throughput rate performance.

The user does not have to worry about any power-up times with

the AD7440/AD7450A remaining fully powered up all the time.

SCLK

SDATA

THREE-STATE

Figure 41 shows the general diagram of the operation of the

AD7440/AD7450A in this mode. The conversion is initiated on

the falling edge of CS, as described in the Serial Interface

section. To ensure the part remains fully powered up,

Figure 42. Entering Power-Down Mode

CS must

remain low until at least 10 SCLK falling edges have elapsed

after the falling edge of

Once

has been brought high in this window of SCLKs, the

part enters power-down, the conversion that was initiated by

the falling edge of

CS.

CS is terminated, and SDATA goes back into

three-state. The time from the rising edge of CS to SDATA

three-state enabled is never greater than t

110

SCLK

SDATA

4 LEADING ZEROS + CONVERSION RESULT

(refer to the Timing

Specifications). If CS is brought high before the second SCLK

falling edge, the part remains in normal mode and does not

power down. This avoids accidental power-down due to glitches

on the CS line.

Figure 41. Normal Mode Operation

If CS

In order to exit this mode of operation and power up the

AD7440/AD7450A again, a dummy conversion is performed.

On the falling edge of

is brought high any time after the 10th SCLK falling edge,

but before the 16th SCLK falling edge, the part remains

powered up but the conversion terminates and SDATA goes

back into three-state. Sixteen serial clock cycles are required to

complete the conversion and access the complete conversion

result.

CS, the device begins to power up and

continues to power up as long as CS is held low until after the

falling edge of the 10th SCLK. The device is fully powered up

after 1 μs has elapsed and, as shown in

Figure 43, valid data

results from the next conversion.

may idle high until the next conversion or may idle

low until sometime prior to the next conversion. Once a data

transfer is complete, when SDATA has returned to three-state,

another conversion can be initiated after the quiet time, tQUIET,

has elapsed by again bringing CS low.

SCLK

SDATA

THIS PART IS FULLY POWERED

UP WITH VIN FULLY ACQUIRED

PART BEGINS

TO POWER UP

INVALID DATA

VALID DATA

tPOWER-UP

Figure 43. Exiting Power-Down Mode

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