VMV3 datasheet(95/212 Pages) MICROSEMI

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Military ProASIC3/EL Low Power Flash FPGAs

Revision 3

2-81

HSTL Class II

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).

Military ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a

push-pull output buffer.

Timing Characteristics

Table 2-139 • Minimum and Maximum DC Input and Output Levels

HSTL Class II

VIL

VIH

VOL

VOH

IOL IOH IOSL

IOSH

IIL1 IIH2

Drive

Strength

Min.

Max.

Min.

Max.

Min.

VmA mA

Max.

mA3

Max.

mA3

µA4 µA4

15 mA5

–0.3

VREF – 0.1 VREF + 0.1

3.6

0.4

VCCI – 0.4 15 15

15 15

Notes:

1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at 100°C junction temperature and maximum voltage.

4. Currents are measured at 125°C junction temperature.

5. Output drive strength is below JEDEC specification.

Figure 2-21 • AC Loading

Table 2-140 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

CLOAD (pF)

VREF – 0.1

VREF + 0.1

0.75

Note:

*Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points.

Test Point

20 pF

HSTL

Class II

VTT

Table 2-141 • HSTL Class II

Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 1.4 V, VREF = 0.75 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

tDOUT

tDP

tDIN

tPY

tEOUT

tZL

tZH

tLZ

tHZ

tZLS

tZHS

Units

Std.

0.80

3.00

0.05

2.76

0.52

3.05

2.69

–

5.25

4.89

–1

0.68

2.55

0.05

2.34

0.44

2.59

2.28

–

4.47

4.16

Note:

For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

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