ADP7105ACPZ-R2 datasheet(19/28 Pages) AD

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Data Sheet

ADP7105

Rev. 0 | Page 19 of 28

PROGRAMMABLE UNDERVOLTAGE LOCKOUT

(UVLO)

The ADP7105 uses the EN/UVLO pin to enable and disable the

VOUT pin under normal operating conditions. As shown in

Figure 65, when a rising voltage on EN/UVLO crosses the upper

threshold, VOUT turns on. When a falling voltage on EN/UVLO

crosses the lower threshold, VOUT turns off. The hysteresis of

the EN/UVLO threshold is determined by the Thevenin

equivalent resistance in series with the EN/UVLO pin.

Figure 65. Typical VOUT Response to EN/UVLO Pin Operation

The upper and lower thresholds are user programmable and can

be set using two resistors. When the EN/UVLO pin voltage is

below 1.23 V, the LDO is disabled. When the EN/UVLO pin

voltage transitions above 1.23 V, the LDO is enabled and 10 µA

hysteresis current is sourced out of the pin, raising the voltage

and thus providing threshold hysteresis. Typically, two external

resistors program the minimum operational voltage for the

LDO. The resistance values, R1 and R2, can be determined from

the following:

R1 = VHYS/10 μA

R2 = 1.23 V × R1/(VIN − 1.23 V)

where:

VHYS is the desired EN/UVLO hysteresis level.

VIN is the desired turn-on voltage.

Hysteresis can also be achieved by connecting a resistor in series

with the EN/UVLO pin. For the example shown in Figure 66,

the enable threshold is 2.46 V with a hysteresis of 1 V.

Figure 66. Typical EN/UVLO Pin Voltage Divider

Figure 65 shows the typical hysteresis of the EN/UVLO pin.

This prevents on/off oscillations that can occur due to noise

on the EN/UVLO pin as it passes through the threshold points.

SOFT START FUNCTION

For applications that require a controlled startup, the ADP7105

provides a programmable soft start function. Programmable

soft start is useful for reducing inrush current upon startup and

for providing voltage sequencing. To implement soft start, connect

a small ceramic capacitor from SS to GND. Upon startup, a

1 µA current source charges this capacitor. The ADP7105

start-up output voltage is limited by the voltage at SS, providing

a smooth ramp-up to the nominal output voltage. The soft start

time is calculated by

tSS = VREF × (CSS/ISS)

where:

tSS is the soft start delay.

VREF is the 1.22 V reference voltage.

CSS is the soft start capacitance between SS and GND.

ISS is the current sourced from SS (1 µA).

When the ADP7105 is disabled (by driving EN low), the soft

start capacitor is discharged to GND through an internal 5 kΩ

resistor.

Figure 67. Typical Start-Up Behavior

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

1.25

1.50

1.75

2.00

EN/UVLO (V)

2.25

2.50

2.75

3.00

1.00

VOUT, EN/UVLO RISE

VOUT, EN/UVLO FALL

VOUT = 5V

VIN = 8V

VOUT

VIN

GND

SENSE

EN/

UVLO

100k

Ω

100k

Ω

100k

Ω

COUT

1µF

CIN

1µF

OFF

CSS

TIME (ms)

2.7nF

0nF

6.8nF

10nF

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