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ADuC7023BCPZ62I-R7 数据表(PDF) 52 Page - Analog Devices

部件名 ADuC7023BCPZ62I-R7
功能描述  Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU with Enhanced IRQ Handler
PDF  96 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADuC7023BCPZ62I-R7 数据表(HTML) 52 Page - Analog Devices

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ADuC7023
Data Sheet
| Page 52 of 96
GP2PAR Register
Name
GP2PAR
Address
0xFFFFF44C
Default value
0x00000000
Access
Read/write
Function
GP2PAR programs the parameters for Port 0,
Port 1, and Port 2. Note that the GP2DAT
MMR must always be written after changing
the GP2PAR MMR.
Table 57. GPxPAR MMR Bit Descriptions
Bit
Description
31
Reserved.
30 to 29
Drive strength Px.7
28
Pull-up disable Px.7.
27
Reserved.
26 to 26
Drive strength Px.6
24
Pull-up disable Px.6.
23
Reserved.
22 to 21
Drive strength Px.5
20
Pull-up disable Px.5.
19
Reserved.
18 to 17
Drive strength Px.4
16
Pull-up disable Px.4.
15
Reserved.
14 to 13
Drive strength Px.3
12
Pull-up disable Px.3.
11
Reserved.
10 to 9
Drive strength Px.2
8
Pull-up disable Px.2.
7
Reserved.
6 to 5
Drive strength Px.1
4
Pull-up disable Px.1.
3
Reserved.
2 to 1
Drive strength Px.0
0
Pull-up disable Px.0.
Table 58. GPIO Drive Strength Control Bits Descriptions
Control Bits Value
Description
00
Medium drive strength.
01
Low drive strength.
1x
High drive strength.
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
–24
–18
–12
–6
0
6
12
18
24
LOAD CURRENT (mA)
HIGH DRIVE STRENGTH
MEDIUM DRIVE STRENGTH
LOW DRIVE STRENGTH
Figure 37. Programmable Strength for High Level
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–24
–18
–12
–6
0
6
12
18
24
LOAD CURRENT (mA)
HIGH DRIVE STRENGTH
MEDIUM DRIVE STRENGTH
LOW DRIVE STRENGTH
Figure 38. Programmable Strength for Low Level
The drive strength bits can be written one time only after reset.
More writing to related bits has no effect on changing drive
strength. The GPIO drive strength and pull-up disable is not
always adjustable for the GPIO port. Some control bits cannot be
changed (see Table 59).
Table 59. GPxPAR Control Bits Access Descriptions1
Bit
GP0PAR
GP1PAR
GP2PAR
31
Reserved
Reserved
Reserved
30 to 29
R/W
R/W
Reserved
28
R/W
R/W
Reserved
27
Reserved
Reserved
Reserved
26 to 26
R/W
R/W
Reserved
24
R/W
R/W
Reserved
23
Reserved
Reserved
Reserved
22 to 21
R/W
R (b00)
Reserved
20
R/W
R/W
Reserved
19
Reserved
Reserved
Reserved
18 to 17
R (b00)
R (b00)
R (b00)
16
R/W
R/W
R/W
15
Reserved
Reserved
Reserved
14 to 13
R (b00)
R (b00)
R (b00)
12
R/W
R/W
R/W
11
Reserved
Reserved
Reserved
Rev. E



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