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ADuC7023BCPZ62I-R7 数据表(PDF) 73 Page - Analog Devices |
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ADuC7023BCPZ62I-R7 数据表(HTML) 73 Page - Analog Devices |
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73 / 96 page  Data Sheet ADuC7023 | Page 73 of 96 On power-up, PWMCON1 defaults to 0x0012 (HOFF = 1 and HMODE = 1). All GPIO pins associated with the PWM are configured in PWM mode by default (see Table 86). Clear the PWM trip interrupt by writing any value to the PWMCLRI MMR. Note that when using the PWM trip interrupt, clear the PWM interrupt before exiting the ISR. This prevents generation of multiple interrupts. Table 86. PWM Output Selection PWMCON1 MMR1 PWM Outputs2 ENA HOFF POINV DIR PWM0 PWM1 PWM2 PWM3 0 0 X X 1 1 1 1 X 1 X X 1 0 1 0 1 0 0 0 0 0 HS1 LS1 1 0 0 1 HS1 LS1 0 0 1 0 1 0 HS1 LS1 1 1 1 0 1 1 1 1 HS1 LS1 1 X is don’t care. 2 HS = high side, LS = low side. Table 87. Compare Registers Name Address Default Value Access PWM0COM0 0xFFFF0F84 0x0000 R/W PWM0COM1 0xFFFF0F88 0x0000 R/W PWM0COM2 0xFFFF0F8C 0x0000 R/W PWM1COM0 0xFFFF0F94 0x0000 R/W PWM1COM1 0xFFFF0F98 0x0000 R/W PWM1COM2 0xFFFF0F9C 0x0000 R/W PWM2COM0 0xFFFF0FA4 0x0000 R/W PWM2COM1 0xFFFF0FA8 0x0000 R/W Rev. E |
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