MPC8548ECPXAUJC datasheet(70/151 Pages) FREESCALE

70 / 151 page

MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 43 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It

assumes that the DC levels of the clock driver chip is compatible with SerDes reference clock input’s DC

requirement.

Figure 43. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)

Figure 44 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.

Since LVDS clock driver’s common mode voltage is higher than the SerDes reference clock input’s

allowed range (100–400 mV), AC-coupled connection scheme must be used. It assumes the LVDS output

driver features 50-

termination resistor. It also assumes that the LVDS transmitter establishes its own

common mode level without relying on the receiver or other external component.

Figure 44. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)

Figure 45 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.

Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with

the SerDes reference clock input’s DC requirement, AC-coupling must be used. Figure 45 assumes that

the LVPECL clock driver’s output impedance is 50

R1 is used to DC-bias the LVPECL outputs prior



SD_REF_CLK

Clock Driver

100

Differential PWB Trace

Clock driver vendor dependent

source termination resistor

CLK_Out

HCSL CLK Driver Chip



Total 50

Assume clock driver’s

output impedance is about 16



MPC8548E

CLK_Out

SerDes Refer.

CLK Receiver

Clock Driver

SD_REF_CLK

Clock Driver

100

Differential PWB Trace

CLK_Out

LVDS CLK Driver Chip

10 nF

MPC8548E

SerDes Refer.

CLK Receiver



Clock Driver

MPC8548ECPXAUJC 数据表(PDF) 70 Page - Freescale Semiconductor, Inc

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