 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
MPC8548ECPXAUJC 数据表(PDF) 87 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC8548ECPXAUJC 数据表(HTML) 87 Page - Freescale Semiconductor, Inc |
|
|
87 / 151 page  MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 Freescale Semiconductor 87 Serial RapidIO components are included in this requirement. The reference impedance for return loss measurements is 100- resistive for differential return loss and 25- resistive for common mode. Table 66. Receiver AC Timing Specifications—1.25 GBaud Characteristic Symbol Range Unit Notes Min Max Differential input voltage VIN 200 1600 mVp-p Measured at receiver Deterministic jitter tolerance JD 0.37 — UI p-p Measured at receiver Combined deterministic and random jitter tolerance JDR 0.55 — UI p-p Measured at receiver Total jitter tolerance1 JT 0.65 — UI p-p Measured at receiver Multiple input skew SMI — 24 ns Skew at the receiver input between lanes of a multilane link Bit error rate BER — 10–12 —— Unit interval UI 800 800 ps ±100 ppm Note: 1. Total jitter is composed of three components, deterministic jitter, random jitter, and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 53. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects. Table 67. Receiver AC Timing Specifications—2.5 GBaud Characteristic Symbol Range Unit Notes Min Max Differential input voltage VIN 200 1600 mVp-p Measured at receiver Deterministic jitter tolerance JD 0.37 — UI p-p Measured at receiver Combined deterministic and random jitter tolerance JDR 0.55 — UI p-p Measured at receiver Total jitter tolerance1 JT 0.65 — UI p-p Measured at receiver Multiple input skew SMI — 24 ns Skew at the receiver input between lanes of a multilane link Bit error rate BER — 10–12 — Unit interval UI 400 400 ps ±100 ppm Note: 1. Total jitter is composed of three components, deterministic jitter, random jitter, and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 53. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
