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AD7674AST 数据表(PDF) 6 Page - Analog Devices

部件名 AD7674AST
功能描述  18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC
PDF  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD7674AST 数据表(HTML) 6 Page - Analog Devices

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AD7674
Rev. A | Page 6 of 28
Table 4. Serial Clock Timings in Master Read after Convert
DIVSCLK[1]
Symbol
0
0
1
1
Unit
DIVSCLK[0]
0
1
0
1
SYNC to SCLK First Edge Delay Minimum
t18
3
17
17
17
ns
Internal SCLK Period Minimum
t19
25
60
120
240
ns
Internal SCLK Period Maximum
t19
40
80
160
320
ns
Internal SCLK HIGH Minimum
t20
12
22
50
100
ns
Internal SCLK LOW Minimum
t21
7
21
49
99
ns
SDOUT Valid Setup Time Minimum
t22
4
18
18
18
ns
SDOUT Valid Hold Time Minimum
t23
2
4
30
89
ns
SCLK Last Edge to SYNC Delay Minimum
t24
3
60
140
300
ns
Busy High Width Maximum (Warp)
t28
1.75
2.5
4
7
μs
Busy High Width Maximum (Normal)
t28
2
2.75
4.25
7.25
μs
Busy High Width Maximum (Impulse)
t28
2.25
3
4.5
7.5
μs



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