AD7674AST datasheet(23/28 Pages) AD

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AD7674

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degradation of the conversion result could occur. This is

particularly important during the second half of the conversion

phase because the AD7674 provides error correction circuitry

that can correct for an improper bit decision made during the

first half of the conversion phase. For this reason, it is

recommended that when an external clock is being provided, it

is a discontinuous clock that only toggles when BUSY is low or,

more importantly, that it does not transition during the latter

half of BUSY high.

External Discontinuous Clock Data Read after

Conversion

Though maximum throughput cannot be achieved using this

mode, it is the most recommended of the serial slave modes.

Figure 42 shows the detailed timing diagrams of this method.

After a conversion is complete, indicated by BUSY returning

low, the result of this conversion can be read while both CS and

RD are low. Data is shifted out MSB first with 18 clock pulses,

and is valid on the rising and falling edge of the clock.

Among the advantages of this method, the conversion

performance is not degraded because there are no voltage

transients on the digital interface during the conversion process.

Also, data can be read at speeds up to 40 MHz, accommodating

both slow digital host interface and the fastest serial reading.

Finally, in this mode only, the AD7674 provides a daisy-chain

feature using the RDC/SDIN input pin to cascade multiple

converters together. This feature is useful for reducing

component count and wiring connections when desired (for

instance, in isolated multiconverter applications).

An example of the concatenation of two devices is shown in

Figure 44. Simultaneous sampling is possible by using a

common CNVST signal. It should be noted that the RDC/SDIN

input is latched on the edge of SCLK opposite the one used to

shift out data on SDOUT. Thus, the MSB of the upstream

converter follows the LSB of the downstream converter on the

next SCLK cycle.

SCLK

SDOUT

D17

D16

D15

X17

X16

X15

Y17

Y16

BUSY

SDIN

INVSCLK = 0

X17

X16

EXT/INT = 1

RD = 0

t35

t36 t37

t31

t32

t34

t16

t33

03083-0-042

Figure 42. Slave Serial Data Timing for Reading (Read after Convert)

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