PE97632 datasheet(13/15 Pages) PSEMI

部件名	PE97632

功能描述	3.5 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications

PDF	15 Pages

Scroll/Zoom	100%

制造商	PSEMI [Peregrine Semiconductor]

网页	http://www.psemi.com

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13 / 15 page

Product Specification

PE97632

Document No. 70-0205-07 │ www.psemi.com

Page 13 of 15

Enhancement Register

Figure 10. Serial Interface Mode Timing Diagram

The functions of the enhancement register bits are shown below with all bits active “high”.

Table 10. Enhancement Register Bit Functionality

Bit Function

Description

Bit 0

Reserve **

Reserved.

Bit 1

Reserve **

Reserved.

Bit 2

fp output

Drives the M counter output onto the Dout output.

Bit 3

Power down

Power down of all functions except programming interface.

Bit 4

Counter load

Immediate and continuous load of counter programming.

Bit 5

MSEL output

Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.

Bit 6

fc output

Drives the reference counter output onto the Dout output.

Bit 7

LD Disable

Disables the LD pin for quieter operation.

** Program to 0

DHLD

DSU

ClkH

ClkL

CWR

WRC

E_WR

Sdata

Sclk

S_WR

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