Product Specification

PE97632

Page 4 of 15

©2006-2011 Peregrine Semiconductor Corp. All rights reserved.

Document No. 70-0205-07 │ UltraCMOS™ RFIC Solutions

47

Both

Input

Prescaler input from the VCO, 3.5 GHz max frequency. A 22 pF coupling capacitor should

be placed as close as possible to this pin and terminated with a 50 Ω resistor to ground.

48

Both

Input

Prescaler complementary input. A 22pF bypass capacitor should be placed as close as

possible to this pin and be connected in series with a 50 Ω resistor to ground.

49

GND

Downbond Ground

50

CEXT

Both

Output

Logical “NAND” of PD_

U and PD_D terminated through an on chip, 2 kΩ series resistor.

Connecting Cext to an external capacitor will low pass filter the input to the inverting

amplifier used for driving LD.

51

LD

Both

Output

Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high

impedance, otherwise LD is a logic low (“0”).

52

Both

Output

Data out function, enabled in enhancement mode.

53

(Note 1)

54

GND

Downbond Ground

55

PD_

D

Both

Output

PD_

56

NC

Both

(Note 3)

No Connect

57

PD_

U

Both

Output

PD_

58

GND

Downbond Ground

59

(Note 1)

60

(Note 1)

61

GND

Downbond Ground

62

Both

Input

Reference frequency input.

63

(Note 1)

64

(Note 1)

GND

Downbond Ground

65

Enh

Both

Input

Enhancement mode. When asserted low (“0”), enhancement register bits are functional.

66

NC

Both

(Note 3)

No Connect

67

MS2_SEL

Both

Input

MASH 1-1 select. “High” selects MASH 1-1 mode. “Low” selects the MASH 1-1-1 mode.

68

RND_SEL

Both

Input

K register LSB toggle enable. “1” enables the toggling of LSB. This is equivalent to having

an additional bit for the LSB of K register. The frequency offset as a result of enabling this

2. All digital input pins have 70 kΩ pull-down resistors to ground.

3. No Connect pins can be left open or floating.

46

(Note 1)

Pin No.

Pin Name

Valid Mode

Type

Description