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ADE7933 数据表(PDF) 110 Page - Analog Devices

部件名 ADE7933
功能描述  Isolated Energy Metering Chipset for Polyphase Shunt Meters
PDF  120 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7933 数据表(HTML) 110 Page - Analog Devices

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ADE7978/ADE7933/ADE7932
Data Sheet
Rev. 0 | Page 110 of 120
Table 47. PHSTATUS Register (Address 0xE600)
Bits
Bit Name
Default Value
Description
[2:0]
Reserved
000
Reserved. These bits are always set to 0.
3
OIPHASE[0]
0
When this bit is set to 1, the Phase A current generates Bit 17 (OI) in the STATUS1 register.
4
OIPHASE[1]
0
When this bit is set to 1, the Phase B current generates Bit 17 (OI) in the STATUS1 register.
5
OIPHASE[2]
0
When this bit is set to 1, the Phase C current generates Bit 17 (OI) in the STATUS1 register.
[8:6]
Reserved
000
Reserved. These bits are always set to 0.
9
OVPHASE[0]
0
When this bit is set to 1, the Phase A voltage generates Bit 18 (OV) in the STATUS1 register.
10
OVPHASE[1]
0
When this bit is set to 1, the Phase B voltage generates Bit 18 (OV) in the STATUS1 register.
11
OVPHASE[2]
0
When this bit is set to 1, the Phase C voltage generates Bit 18 (OV) in the STATUS1 register.
12
VSPHASE[0]
0
When this bit is set to 1, the Phase A voltage generates Bit 16 (sag) in the STATUS1 register.
13
VSPHASE[1]
0
When this bit is set to 1, the Phase B voltage generates Bit 16 (sag) in the STATUS1 register.
14
VSPHASE[2]
0
When this bit is set to 1, the Phase C voltage generates Bit 16 (sag) in the STATUS1 register.
15
Reserved
0
Reserved. This bit is always set to 0.
Table 48. PHNOLOAD Register (Address 0xE608)
Bits
Bit Name
Default Value
Description
0
NLPHASE[0]
0
0: Phase A is out of the no load condition based on the total active and reactive powers.
1: Phase A is in the no load condition based on the total active and reactive powers. This
bit is set together with Bit 0 (NLOAD) in the STATUS1 register.
1
NLPHASE[1]
0
0: Phase B is out of the no load condition based on the total active and reactive powers.
1: Phase B is in the no load condition based on the total active and reactive powers. This
bit is set together with Bit 0 (NLOAD) in the STATUS1 register.
2
NLPHASE[2]
0
0: Phase C is out of the no load condition based on the total active and reactive powers.
1: Phase C is in the no load condition based on the total active and reactive powers. This
bit is set together with Bit 0 (NLOAD) in the STATUS1 register.
3
FNLPHASE[0]
0
0: Phase A is out of the no load condition based on the fundamental active and reactive
powers.
1: Phase A is in the no load condition based on the fundamental active and reactive
powers. This bit is set together with Bit 1 (FNLOAD) in the STATUS1 register.
4
FNLPHASE[1]
0
0: Phase B is out of the no load condition based on the fundamental active and reactive
powers.
1: Phase B is in the no load condition based on the fundamental active and reactive
powers. This bit is set together with Bit 1 (FNLOAD) in the STATUS1 register.
5
FNLPHASE[2]
0
0: Phase C is out of the no load condition based on the fundamental active and reactive
powers.
1: Phase C is in the no load condition based on the fundamental active and reactive
powers. This bit is set together with Bit 1 (FNLOAD) in the STATUS1 register.
6
VANLPHASE[0]
0
0: Phase A is out of the no load condition based on the apparent power.
1: Phase A is in the no load condition based on the apparent power. This bit is set together
with Bit 2 (VANLOAD) in the STATUS1 register.
7
VANLPHASE[1]
0
0: Phase B is out of the no load condition based on the apparent power.
1: Phase B is in the no load condition based on the apparent power. This bit is set together
with Bit 2 (VANLOAD) in the STATUS1 register.
8
VANLPHASE[2]
0
0: Phase C is out of the no load condition based on the apparent power.
1: Phase C is in the no load condition based on the apparent power. This bit is set together
with Bit 2 (VANLOAD) in the STATUS1 register.
[15:9]
Reserved
000 0000
Reserved. These bits are always set to 0.



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