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PIC12F635ESL 数据表(PDF) 74 Page - Microchip Technology |
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PIC12F635ESL 数据表(HTML) 74 Page - Microchip Technology |
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74 / 234 page ![]() PIC12F635/PIC16F636/639 DS41232D-page 72 © 2007 Microchip Technology Inc. FIGURE 7-3: COMPARATOR C1 OUTPUT BLOCK DIAGRAM (PIC16F636/639) FIGURE 7-4: COMPARATOR C2 OUTPUT BLOCK DIAGRAM (PIC16F636/639) DQ EN To C1OUT pin RD CMCON0 Set C1IF bit Q3*RD CMCON0 Reset To Data Bus C1INV DQ EN CL Q1 Note 1: Q1 and Q3 are phases of the four-phase system clock (FOSC). 2: Q1 is held high during Sleep mode. C1 C2SYNC DQ EN To C2OUT pin RD CMCON0 Set C2IF bit Q3*RD CMCON0 Reset To Data Bus C2INV Timer1 clock source(1) 0 1 To Timer1 Gate DQ DQ EN CL Q1 Note 1: Comparator output is latched on falling edge of Timer1 clock source. 2: Q1 and Q3 are phases of the four-phase system clock (FOSC). 3: Q1 is held high during Sleep mode. C2 |
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