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PIC12F635ESL 数据表(PDF) 83 Page - Microchip Technology |
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PIC12F635ESL 数据表(HTML) 83 Page - Microchip Technology |
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83 / 234 page ![]() © 2007 Microchip Technology Inc. DS41232D-page 81 PIC12F635/PIC16F636/639 7.9 Comparator Gating Timer1 This feature can be used to time the duration or inter- val of analog events. Clearing the T1GSS bit of the CMCON1 register will enable Timer1 to increment based on the output of the comparator (or Comparator C2 for PIC16F636/639). This requires that Timer1 is on and gating is enabled. See Section 6.0 “Timer1 Module with Gate Control” for details. It is recommended to synchronize the comparator with Timer1 by setting the CxSYNC bit when the comparator is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if the comparator changes during an increment. 7.10 Synchronizing Comparator Output to Timer1 The comparator (or Comparator C2 for PIC16F636/639) output can be synchronized with Timer1 by setting the CxSYNC bit of the CMCON1 register. When enabled, the comparator output is latched on the falling edge of the Timer1 clock source. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure 7-2) and the Timer1 Block Diagram (Figure 6-1) for more information. Note: References to the comparator in this section specifically are referring to Comparator C2 on the PIC16F636/639. Note: References to the comparator in this section specifically are referring to Comparator C2 on the PIC16F636/639. |
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