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PIC12F635ESL 数据表(PDF) 80 Page - Microchip Technology |
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PIC12F635ESL 数据表(HTML) 80 Page - Microchip Technology |
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80 / 234 page  PIC12F635/PIC16F636/639 DS41232D-page 78 © 2007 Microchip Technology Inc. FIGURE 7-8: COMPARATOR INTERRUPT TIMING W/O CMCON0 READ FIGURE 7-9: COMPARATOR INTERRUPT TIMING WITH CMCON0 READ Note 1: If a change in the CMCON0 register (CxOUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CxIF of the PIR1 register interrupt flag may not get set. 2: When either comparator is first enabled, bias circuitry in the Comparator module may cause an invalid output from the comparator until the bias circuitry is stable. Allow about 1 μs for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts. Q1 Q3 CIN+ CxOUT Set CxIF (level) CxIF TRT reset by software Q1 Q3 CIN+ CxOUT Set CxIF (level) CxIF TRT reset by software cleared by CMCON0 read |
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