LPC2104FBD48 datasheet(12/41 Pages) NXP

12 / 41 page

LPC2104_2105_2106_7

Product data sheet

Rev. 07 — 20 June 2008

12 of 41

NXP Semiconductors

LPC2104/2105/2106

Single-chip 32-bit microcontrollers

6.5 Interrupt controller

The Vectored Interrupt Controller (VIC) accepts all of the Interrupt Request (IRQ) inputs

and categorizes, them as FIQ, vectored IRQ, and non-vectored IRQ as deﬁned by

programmable settings. The programmable assignment scheme means that priorities of

interrupts from the various peripherals can be dynamically assigned and adjusted.

Fast Interrupt reQuest (FIQ) has the highest priority. If more than one request is assigned

to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor.

The fastest possible FIQ latency is achieved when only one request is classiﬁed as FIQ,

because then the FIQ service routine can simply start dealing with that device. But if more

than one request is assigned to the FIQ class, the FIQ service routine can read a word

from the VIC that identiﬁes which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned

to this category. Any of the interrupt requests can be assigned to any of the 16 vectored

IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to produce

the IRQ signal to the ARM processor. The IRQ service routine can start by reading a

VIC provides the address of the highest-priority requesting IRQs service routine,

otherwise it provides the address of a default routine that is shared by all the non-vectored

IRQs. The default routine can read another VIC register to see what IRQs are active.

6.5.1 Interrupt sources

Table 4 lists the interrupt sources for each peripheral function. Each peripheral device has

one interrupt line connected to the Vectored Interrupt Controller, but may have several

internal interrupt ﬂags. Individual interrupt ﬂags may also represent more than one

interrupt source.

Table 4.

Interrupt sources

Block

Flag(s)

VIC channel #

WDT

Watchdog Interrupt (WDINT)

Reserved for software interrupts only

ARM Core

EmbeddedICE, DbgCommRx

ARM Core

EmbeddedICE, DbgCommTx

Timer 0

Match 0 to 3 (MR0, MR1, MR2, MR3)

Capture 0 to 2 (CR0, CR1, CR2)

Timer 1

Match 0 to 3 (MR0, MR1, MR2, MR3)

Capture 0 to 3 (CR0, CR1, CR2, CR3)

UART 0

Rx Line Status (RLS)

Transmit Holding Register empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

Auto-Baud Time-Out (ABTO)[1]

End of Auto-Baud (ABEO)[1]

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