AM53CF94 datasheet(29/76 Pages) AMD

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P R E L I M I N A R Y

AMD

Am53CF94/Am53CF96

Deassertion Delay

SOFREG

FASTCLK

REQ/ACK

Bits 7:6

Ctrl 3, Bit 3

Input CLK Cycles

Default – 0 cycles

1/2 cycle early

1 cycle delay

1/2 cycle delay

Default – 0 cycles

1/2 cycle delay

1 cycle delay

1 1/2 cycles delay

SOFREG – Bits 5:4 – RAA 1:0

These bits may be programmed to control the assertion

delay of the

REQ and ACK signals during synchronous

transfers. Unlike deassertion delay, assertion delay is

independent of the FASTCLK setting.

Assertion Delay

SOFREG

REQ/ACK

Bits 5:4

Input CLK Cycles

Default – 0 cycles

1/2 cycle delay

1 cycle delay

1 1/2 cycles delay

SOFREG – Bits 3:0 – SO 3:0 – Synchronous

Offset 3:0

The SO 3:0 bits are the binary coded value of the num-

ber of bytes that can be sent to (or received from) the

SCSI bus without an

ACK (or REQ) signal. A zero value

designates Asynchronous xfer, while a non-zero value

designates the number of bytes for synchronous

transfer.

Control Register One (08H) Read/Write

Control Register One

CNTLREG1

Address: 08H

Type: Read/Write

76543

210

ETM

DISR

PTE

PERE

STE

CID2

CID1

CID0

0000

Disable Interrupt on SCSI Reset

Parity Test Enable

Parity Error Reporting Enable

Self Test Enable

Chip ID 2:0

Extended Timing Mode

17348B-28

The Control Register 1 (CNTLREG1) sets up the device

with various operating parameters.

CNTLREG1 – Bit 7 – ETM – Extended Timing Mode

Enabling this feature will increase the minimum setup

time for data being transmitted on the SCSI bus. This bit

should only be set if the external cabling conditions pro-

duce SCSI timing violations. FASTCLK operation is

unaffected by this feature.

CNTLREG1 – Bit 6 – DISR – Disable Interrupt on

SCSI Reset

The DISR bit masks the reporting of the SCSI reset.

When the DISR bit is set and a SCSI reset is asserted,

the device will disconnect from the SCSI bus and remain

idle without interrupting the host processor. When the

DISR bit is reset and a SCSI reset is asserted the device

will respond by interrupting the host processor. The

DISR bit is reset to zero by a hard or soft reset.

CNTLREG1 – Bit 5 – PTE – Parity Test Enable

The PTE bit is for test use only. When the PTE bit is set

the parity on the output (SCSI or host processor) bus is

forced to the value of the MSB (bit 7) of the output data

from the internal FIFO. This allows parity errors to be

created to test the hardware and software. The PTE bit

is reset to zero by a hard or soft reset. This bit should not

be set in normal operation.

CNTLREG1 – Bit 4 – PERE – Parity Error Report-

ing Enable

The PERE bit enables the checking and reporting of par-

ity errors on incoming SCSI bytes during the information

transfer phase. When the PERE bit set and bad parity is

detected, the PE bit in the STATREG is will be set but an

interrupt will not be generated. In the Initiator mode the

ATN signal will also be asserted on the SCSI bus. When

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