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AM53CF94 数据表(PDF) 35 Page - Advanced Micro Devices |
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AM53CF94 数据表(HTML) 35 Page - Advanced Micro Devices |
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35 / 76 page ![]() P R E L I M I N A R Y AMD 35 Am53CF94/Am53CF96 4 Control Register Four CNTLREG4 Address: 00H 765 3 210 GE1 GE0 PWD RES RES (R) RAE(W) RADE RES NU 000 0 X X GLITCH EATER Power-Down Reserved RES (R)/Active Negation Ctl (W) Active Negation Ctl. Transfer Count Test Enable Control Register Four (0DH) 17348B-33 X0 This register is used to control several AMD proprietary features implemented in the Am53CF94/96. At power up, this register will show a ‘0’ value on all bits except bit 4. CNTLREG4 – Bit 7:6 – GE1:0 – GLITCH EATER The GLITCH EATER circuitry has been implemented on all SCSI input lines and are controlled by bits 7and 6. The valid signal window may be adjusted by setting the bits in the combinations listed below. CNTLREG4 CNTLREG4 Bit 7 Bit 6 Single- GE1 GE0 ended Differential 0 0 12 ns 0 ns 1 0 25 ns 25 ns 0 1 35 ns 35 ns 1 1 0 ns 12 ns CNTLREG4 – Bit 5 – PWD – Power-Down Feature Setting this bit to ‘1’ will enable AMD’s exclusive power- down feature. This will turn off the input buffers on all the SCSI bus signal lines to reduce power consumption dur- ing the chip’s sleep mode. CNTLREG4 – Bit 4 – RES This bit is reserved for internal use. CNTLREG4 – Bit 3 (Read Only) – RES This bit is reserved for internal use. CNTLREG4 – Bit 3 (Write Only) – RAE – Active Negation Control CNTLREG4 – Bit 2 – RADE – Active Negation Control Bits 2 and 3 control the Active Negation Drivers which may be enabled on REQ, ACK, or DATA lines. The fol- lowing table shows the programming options for this feature: CNTLREG4 CNTLREG4 Bit 3 Bit 2 Function Selected RAE RADE 0 0 Active Negation Disabled 1 0 Active Negation on REQ and ACK only –– 1 Active Negation on REQ, ACK and DATA –– = don’t care CNTLREG4 – Bit 1 – RES This bit is reserved for internal use. CNTLREG4 – Bit 0 – NU – Not Used The NCR53CF94/96 uses this bit to control back-to- back transfers. This bit may be read or written but is not used by the Am53CF94/96. Back-to-Back transfers are always enabled. |
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