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AM79C960 数据表(PDF) 63 Page - Advanced Micro Devices |
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AM79C960 数据表(HTML) 63 Page - Advanced Micro Devices |
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63 / 127 page  P R E L I M I N A R Y AMD 1-405 Am79C960 TXSTRT is set by the MAC Unit and cleared by writing a “1”, set- ting RESET or setting the STOP bit. Writing a “0” has no effect. 2 TXSTRTM Transmit Start Mask. If TXSTRTM is set, the TXSTRT bit in CSR4 will be masked and will not set INTR flag in CSR0. TXS-TRTM is set by RESET and is not affected by STOP. 1 JAB Jabber Error is set when the PCnet-ISA controller Twisted- pair MAU function exceeds an allowed transmission limit. Jab- ber is set by the TMAU cell and can only be asserted in 10BASE-T mode. When JAB is set, IRQ is asserted if IENA = 1 and the mask bit JABM (CSR4.0) is clear. The JAB bit can be reset even if the jabber condition is still present. JAB is set by the TMAU circuit and cleared by writing a “1”. Writ- ing a “0” has no effect. JAB is also cleared by RESET or setting the STOP bit. 0 JABM Jabber Error Mask. If JABM is set, the JAB bit in CSR4 will be masked and will not set INTR flag in CSR0. JABM is set by RESET and is not affected by STOP. CSR6: RCV/XMT Descriptor Table Length Bit Name Description 15-12 TLEN Contains a copy of the transmit encoded ring length (TLEN) field read from the initialization block during PCnet-ISA controller in- itialization. This field is written during the PCnet-ISA controller initialization routine. Read accessible only when STOP bit is set. Write operations have no effect and should not be performed. TLEN is only defined after initialization. 11-8 RLEN Contains a copy of the receive encoded ring length (RLEN) read from the initialization block dur- ing PCnet-ISA controller initiali- zation. This field is written during the PCnet-ISA controller initiali- zation routine. Read accessible only when STOP bit is set. Write operations have no effect and should not be performed. RLEN is only defined after initialization. 7-0 RES Reserved locations. Read as zero. Write operations should not be performed. CSR8: Logical Address Filter, LADRF[15:0] Bit Name Description 15-0 LADRF[15:0] Logical Address Filter, LADRF [15:0]. Undefined until initialized either automatically by loading the initialization block or directly by an I/O write to this register. Read/write accessible only when STOP bit is set. CSR9: Logical Address Filter, LADRF[31:16] Bit Name Description 15-0 LADRF[31:16] Logical Address Filter, LADRF[31:16]. Undefined until initialized either automatically by loading the initialization block or directly by an I/O write to this register. Read/write accessible only when STOP bit is set. CSR10: Logical Address Filter, LADRF[47:32] Bit Name Description 15-0 LADRF[47:32] Logical Address Filter, LADRF[47:32]. Undefined until initialized either automatically by loading the initialization block or directly by an I/O write to this register. Read/write accessible only when STOP bit is set. CSR11: Logical Address Filter, LADRF[63:48] Bit Name Description 15-0 LADRF[63:48] Logical Address Filter, LADRF[63:48]. Undefined until initialized either automatically by loading the initialization block or directly by an I/O write to this register. |
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