AM79C960 datasheet(72/127 Pages) AMD

72 / 127 page

P R E L I M I N A R Y

AMD

1-414

Am79C960

ENTST bit in CSR4 is set, all

writes to this register will auto-

matically perform a decrement

cycle.

When the Bus Activity Timer reg-

ister

(CSR82:

DMABAT)

enabled, the PCnet-ISA control-

ler will relinquish the bus when

either

the

time

specified

DMABAT has elapsed or the

number of transfers specified in

DMABR have occured. When

ENTST (CSR4.15) is asserted,

all writes to this register will auto-

matically perform a decrement

cycle.

Read/write accessible only when

STOP bit is set.

CSR84-85: DMA Address

Bit

Name

Description

31-0

DMABA

DMA Address Register.

This register contains the ad-

dress of system memory for the

current DMA cycle. The Bus In-

terface Unit controls the Address

commands

increment

the

memory address for sequential

operations. The DMABA register

undefined

until

the

first

PCnet-ISA controller DMA op-

eration. When the ENTST bit in

CSR4 is set, all writes to this reg-

ister will automatically perform

an increment cycle.

This register has meaning only if

the PCnet-ISA controller is in Bus

Master Mode.

Read/write accessible only when

STOP bit is set.

CSR86: Buffer Byte Counter

Bit

Name

Description

15-12

RES

Reserved, Read and written with

ones.

11-0

DMABC

DMA Byte Count Register. Con-

tains a Two’s complement of the

current size of the remaining

transmit or receive buffer in

bytes. This register is incre-

mented by the Bus Interface Unit.

The DMABC register is unde-

fined until written. When ENTST

(CSR4.15) is asserted, all writes

to this register will automatically

perform an increment cycle.

Read/write accessible only when

STOP bit is set.

CSR88-89: Chip ID

Bit

Name

Description

31-28

Version. This 4-bit pattern is sili-

con revision dependent.

27-12

Part number. The 16-bit code for

the

PCnet-ISA

controller

0000000000000011b.

11-1

Manufacturer

ID.

The

11-bit

manufacturer code for AMD is

00000000001b. This code is per

the JEDEC Publication 106-A.

Always a logic 1.

This register is exactly the same

as the Chip ID register in the

JTAG description.

CSR92: Ring Length Conversion

Bit

Name

Description

15-0

RCON

Ring Length Conversion Regis-

ter. This register performs a ring

length conversion from an en-

coded value as found in the

initialization block to a Two’s

complement value used for inter-

nal counting. By writing bits

15-12 with an encoded ring

length, a Two’s complemented

value is read. The RCON register

is undefined until written.

Read/write accessible only when

STOP bit is set.

CSR94:Transmit Time Domain Reflectometry

Count

Bit

Name

Description

15-10

RES

Reserved locations. Read and

written as zero.

9-0

XMTTDR

Time Domain Reflectometry re-

flects the state of an internal

counter that counts from the start

of transmission to the occurrence

of loss of carrier. TDR is incre-

mented at a rate of 10 MHz.

Read

accessible

only

when

STOP bit is set. Write operations

are ignored. XMTTDR is cleared

by RESET.

AM79C960 数据表(PDF) 72 Page - Advanced Micro Devices

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