AM79C960 datasheet(125/127 Pages) AMD

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B-1

Am79C960

Recommendation for Reducing

Noise Injection

APPENDIX B

DECOUPLING LOW-PASS R/C

FILTER DESIGN

The PCnet-ISA controller is an integrated, single-chip

Ethernet controller, which contains both digital and ana-

log circuitry. The analog circuitry contains a high speed

Phase-Locked Loop (PLL) and Voltage Controlled

Oscillator (VCO). Because of the mixed signal charac-

teristics of this chip, some extra precautions must be

taken into account when designing with this device.

Described in this section is a simple decoupling low-

pass R/C filter that can significantly increase noise im-

munity of the PLL circuit, thus, prevent noise from

disrupting the VCO. Bit error rate, a common measure-

ment of network performance, as a result can be

drastically reduced. In certain cases the bit error rate

can be reduced by orders of magnitude.

Implementation of this filter is not necessary to achieve

a functional product that meets the IEEE 802.3 specifi-

cation and provides adequate performance. However,

this filter will help designers meet those specifications

with more margin.

Digital Decoupling

The DVSS pins that are sinking the most current are

those that provide the ground for the ISA bus output sig-

nals since these outputs require 24 mA drivers. The

DVSS10 and DVSS12 pins provide the ground for the

internal digital logic. In addition, DVSS11 provides

ground for the internal digital and for the Input and

I/O pins.

The CMOS technology used in fabricating the

PCnet-ISA controller employs an n-type substrate. In

this technology, all VDD pins are electrically connected to

each other internally. Hence, in a 4-layer board, when

decoupling between VDD and critical VSS pins, the spe-

cific VDD pin that you connect to is not critical. In fact, the

VDD connection of the decoupling capacitor can be

made directly to the power plane, near the closest VDD

pin to the VSS pin of interest. However, we recommend

that the VSS connection of the decoupling capacitor be

made directly to the VSS pin of interest as shown.

VDD Pin

VSS Pin

PCnet-ISA

via to VDD plane

via to VSS plane

AMD recommends that at least one low-frequency bulk

decoupling capacitor be used in the area of the

PCnet-ISA controller. 22

µF capacitors have worked

well for this. In addition, a total of 4 or 5 0.1

µF capaci-

tors have proven sufficient around the DVSS and DVDD

pins that supply the drivers of the ISA bus output pins.

Analog Decoupling

The most critical pins are the analog supply and ground

pins. All of the analog supply and ground pins are lo-

cated in one corner of the device. Specific requirements

of the analog supply pins are listed below.

AVSS1 and AVDD3

These pins provide the power and ground for the

Twisted Pair and AUI drivers. Hence, they are very

noisy. A dedicated 0.1

µF capacitor between these pins

is recommended.

AVSS2 and AVDD2

These pins are the most critical pins on the PCnet-ISA

controller because they provide the power and ground

for the PLL portion of the chip. The VCO portion of the

PLL is sensitive to noise in the 60–200 kHz. range. To

prevent noise in this frequency range from disrupting the

VCO, AMD strongly recommends that the low-pass filter

shown below be implemented on these pins. Tests us-

ing this filter have shown significantly increased noise

immunity and reduced Bit Error Rate (BER) statistics in

designs using the PCnet-ISA controller.

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