| 数据搜索系统,热门电子元器件搜索 |
|
AM79C940VCW 数据表(PDF) 91 Page - Advanced Micro Devices |
|
|
|||||||||||||||||||||||||||||
AM79C940VCW 数据表(HTML) 91 Page - Advanced Micro Devices |
|
91 / 122 page ![]() AMD 91 Am79C940 DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified (continued) Parameter Symbol Parameter Description Test Conditions Min Max Unit VRXDTH RXD Switching Threshold (Note 4) –35 35 mV VTXH TXD ± and TXP± Output HIGH Voltage DVSS = 0 V DVDD – 0.6 DVDD V VTXL TXD ± and TXP± Output LOW Voltage DVDD = +5 V DVSS DVSS + 0.6 V VTXI TXD ± and TXP± Differential Output Voltage Imbalance –40 +40 mV VTXOFF TXD ± and TXP± Idle Output Voltage DVDD = +5 V 40 mV RTX TXD ± Differential Driver Output Impedance (Note 8) 40 Ω TXP ± Differential Driver Output Impedance (Note 8) 80 Ω Notes: 1. VOH does not apply to open-drain output pins. 2. IIL1 and IIL2 applies to all input only pins except DI±, CI±, and XTAL1. IIL1 = ADD4–0, BE1–0, CS, EAM/R, FDS, RESET, RXDAT, R/W, SCLK. IIL2 = TC, TDI, TCK, TMS. 3. Specified for input only pins with internal pull-ups: TC, TDI, TCK, TMS. 4. IOZ applies to all three-state output pins and bi-directional pins. 5. Test not implemented to data sheet specification. 6. Tested, but to values in excess of limits. Test accuracy not sufficient to allow screening guard bands. 7. During the activation of SLEEP: – The following pins are placed in a high impedance state: SRD, SF/BD, TXDAT, DXCVR, DTV, TDTREQ, RDTREQ, NTR and TDO. – The following I/O pins are placed in a high impedance mode and have their internal TTL level translators disabled: DBUS15–0, EOF, SRDCLK, RXCRS, RXDAT, CLSN, TXEN, STDCLK and TXDAT+. – The following input pin has its internal pull-up and TTL level translator disabled: TC. – The following input pins have their internal TTL level translators disabled and do not have internal pull-ups: CS, FDS, R/ W, ADD4–0, SCLK, BE0, BE1 and EAM/R. – The following pins are pulled low: XTAL1 (XTAL2 feedback is cut off from XTAL1), TXD+, TXD–, TXP+, TXP–, DO+ and DO. – The following pins have their input voltage bias disabled: DI+, DI, CI+ and CI. – AWAKE and RWAKE are reset to zero. IDDSLEEP, with either AWAKE set or RWAKE set, will be much higher and its value remains to be determined. 8. Parameter not tested. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |