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AM79C940VCW 数据表(PDF) 94 Page - Advanced Micro Devices |
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AM79C940VCW 数据表(HTML) 94 Page - Advanced Micro Devices |
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94 / 122 page  AMD 94 Am79C940 AC CHARACTERISTICS (continued) Parameter No. Symbol Parameter Description Test Conditions Min (ns) Max (ns) GPSI Clock Timing 17 tSTDC STDCLK period 99 101 18 tSTDCL STDCLK low pulse width See Note 1 45 19 tSTDCH STDCLK high pulse width 45 20 tSTDCR STDCLK rise time See Note 1 5 21 tSTDCF STDCLK fall time See Note 1 5 22 tSRDC SRDCLK period 85 115 23 tSRDCH SRDCLK HIGH pulse width 38 24 tSRDCL SRDCLK LOW pulse width 38 25 tSRDCR SRDCLK rise time See Note 1 5 26 tSRDCF SRDCLK fall time See Note 1 5 GPSI Timing 70 tTXEND STDCLK ↑ delay to TXEN↑ (CL=50 pF) 70 71 tTXENH TXEN hold time from STDCLK ↑ (CL=50 pF) 5 72 tTXDD STDCLK ↑ delay to TXDAT+ (CL=50 pF) 70 change 73 tTXDH TXDAT+ hold time from (CL=50 pF) 5 STDCLK ↑ 74 tRXDR RXDAT rise time See Note 1 8 75 tRXDF RXDAT fall time See Note 1 8 76 tRXDH RXDAT hold time (SRDCLK ↑ to 25 RXDAT change) 77 tRXDS RXDAT setup time 0 (RXDAT stable to SRDCLK ↑) 78 tCRSL RXCRS low time tSTDC+20 79 tCLSHI CLSN high time tSTDC+30 80 tTXH TXEN or TXDAT ± hold time from 32*tSTDC 96*tSTDC CLSN ↑ 81 tCRSH RXCRS hold time from 0 SRDCLK ↑ EADI Feature Timing 85 tDSFBDR SRDCLK ↓ delay to SF/BD↑ 20 86 tDSFBDF SRDCLK ↓ delay to SF/BD↓ 20 87 tEAMRIS EAM/R invalid setup prior to –150 SRDCLK ↓ after SFD 88 tEAMS EAM setup to SRDCLK ↓ at bit 6 0 of Source Address byte 1 (match packet) 89 tEAMRL EAM/R low time 200 90 tSFBDHIH SF/BD high hold from last 100 SRDCLK ↓ 91 tEARS EAR setup to SRDCLK ↓ at bit 6 0 of message byte 64 (reject normal packet) Note: 1. Not tested but data available upon request. |
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