AM79C981 datasheet(22/40 Pages) AMD

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AMD

PRELIMINARY

1–92

Am79C981

Loopback Test Mode

The IMR+ chip can be programmed to enter Loopback

Mode on all network ports. This is accomplished by first

driving the TEST pin HIGH, then clocking (using the

SCLK pin) a minimum of three 0s into the SI pin. This

causes the IMR+ chip to loop all received data on each

port back to each port’s corresponding transmit outputs.

Specifically, the AUI DI input is passed unaltered to the

AUI DO output, and each RXD input on the twisted pair

ports is passed (unaltered) to the respective TXD and

TXP outputs. Only receive data that passes the required

amplitude squelch criteria is looped back to the transmit

outputs. Note that the data is looped back unaltered,

meaning that no signal retiming or regeneration takes

place. Therefore, any signal distortion present on the re-

ceive data paths will be retransmitted.

In Minimum Mode, the Loopback Test Mode cannot be

accessed. The IMR+ device will return to normal opera-

tion when the TEST pin is again driven LOW.

TEST

SCLK

17306B-11

Figure 6. Programming the IMR+ Device for Loopback Mode

AM79C981 数据表(PDF) 22 Page - Advanced Micro Devices