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AM79C981 数据表(PDF) 27 Page - Advanced Micro Devices |
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AM79C981 数据表(HTML) 27 Page - Advanced Micro Devices |
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27 / 40 page  AMD PRELIMINARY 1–97 Am79C981 SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Max Unit Clock and Reset tX1 X1 Clock Period 49.995 50.005 ns tX1H X1 Clock HIGH 20 30 ns tX1L X1 Clock LOW 20 30 ns tX1R X1 Clock Rise Time – 10 ns tX1F X1 Clock Fall Time – 10 ns tPRST Reset pulse width after power on 150 – µs ( RST pin LOW) tRST Reset pulse width 4 – µs ( RST pin LOW) tRSTSET RST HIGH setup time with 20 – ns respect to X1 Clock tRSTHLD RST LOW hold time with 0 – ns respect to X1 Clock Management Port tSCLK SCLK Clock Period 100 – ns tSCLKH SCLK Clock HIGH 30 – ns tSCLKL SCLK Clock LOW 30 – ns tSCLKR SCLK Clock Rise Time – 10 ns tSCLKF SCLK Clock Fall Time – 10 ns tSISET SI input setup time with respect to SCLK 10 – ns rising edge tSIHLD SI input hold time with 10 – ns respect to SCLK rising edge tSODLY SO output delay with CL = 100 pF – 40 ns respect to SCLK rising edge tX1HCRS X1 rising edge to CRS valid CL = 100 pF 5 40 ns tX1HSTH X1 rising edge to STR HIGH CL = 100 pF – 40 ns tX1HSTL X1 rising edge to STR LOW CL = 100 pF – 40 ns tTESTSET TEST input setup time with respect to 10 – ns SCLK rising edge tTESTHLD TEST input hold time with respect to 10 – ns SCLK rising edge tSTRSET STR setup time 5 – ns tSTRHLD STR hold time 12 – ns Expansion Port tX1HRL X1 rising edge to REQ driven LOW CL = 100 pF 14 40 ns tX1HRH X1 rising edge to REQ driven HIGH CL = 100 pF 14 40 ns tX1HDR X1 rising edge to DAT/JAM driven CL = 100 pF 14 40 ns tX1HDZ X1 rising edge to DAT/JAM not driven CL = 100 pF 14 40 ns |
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