AM85C30 datasheet(3/194 Pages) AMD

3 / 194 page

PREFACE

Thank you for your interest in the SCC, one of the most popular Serial Data ICs available

today. This manual is intended to provide answers to technical questions about the

Am8530H and Am85C30.

If you have already used the Am8530H and are familiar with the previous editions of this

Technical Manual, you will find that some chapters are virtually unchanged. The

Am8030’s functionality, however, has been omitted from this revision since a CMOS

Am8030 was not developed. You can, however, consult the previous Am8030/8530 Tech-

nical Manual revision for information pertaining to Am8030 operation.

Functional descriptions of enhancements added to the Am85C30 have been included in

this Technical Manual revision. These enhancements improve the Am85C30’s functional-

ity and allow it to be used more effectively in high-speed applications. These enhance-

ments include:

s a 10 x 19-bit SDLC/HDLC frame status FIFO array

s a 14-bit SDLC/HDLC frame byte counter

s automatic SDLC/HDLC opening flag transmission

s automatic SDLC/HDLC Tx Underrun/EOM flag resetting

s automatic SDLC/HDLC Tx CRC generator presetting

RTS pin synchronization to closing SDLC/HDLC flag

DTR/REQ deactivation delay significantly reduced

s external PCLK to RxC or TxC synchronization requirement eliminated for PCLK divide-

by-four operation

s complete SDLC/HDLC CRC character reception

s reduced

INT response time

s Write data setup time to rising edge of

WR requirement eliminated

s Write Registers WR3, WR4, WR5, and WR10 made readable

Most users read only chapters that are of interest to them. If you are designing the micro-

computer hardware using the SCC as a peripheral, you will want to read the Applications

Section in Chapter 7. Application notes covering the interfacing of the Am8530H (pre H-

step and CMOS versions only) to the 8086/80186, 68000 processors and Am7960 Data

Coded Transceiver have been included.

As was the case with the NMOS SCC, some points to look out for when using the

Am85C30 are:

s Follow the worksheet for initialization (Chapter 7). Unexplainable operations may occur if

this procedure is not followed.

s Watch out for the Write Recovery time violation. The specification for this (Trc) was

changed on both the H-step and CMOS version. It is now referenced from falling edge to

falling edge of the Read/Write pulse. Trc is spec’d at 4 PCLKs for the NMOS H-step and 3

PCLKs (best case)/3.5 PCLKs for the Am85C30.

s Ensure Mode bits are not changed when writing commands. Each Mode bit affects only

one function and a Command bit entry requires a rewrite of the entire register; therefore,

care must be taken to insure the integrity of the Mode bits whenever a new command is

issued.

s Any unused input pins should be tied high.

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