AM85C30 datasheet(39/194 Pages) AMD

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I/O Programming Functional Description

AMD

3–8

The interrupt protocol is diagrammed in Figure 3–5. In the quiescent state (i.e. no inter-

rupts pending or under service) each SCC on the daisy chain passes its IEI input through

to its IEO output. An interrupt source that requires servicing requests an interrupt by pull-

ing the INT pin Low if the following conditions exist: 1) interrupt source is enabled (i.e., IE

and MIE bits are set to ‘1’), 2) interrupt source is not already under service (i.e., internal

IUS bit set to ‘0’), 3) no higher priority interrupt is under service (i.e., internal IUS bit set to

‘1’), and 4) an interrupt acknowledge cycle is not currently being executed (i.e.,

INTACK

is High).

When the processor responds with an Interrupt Acknowledge cycle all SCCs that have

enabled interrupt sources with an interrupt pending or already under service, hold their

IEO outputs lines Low. When RD goes Low, only the highest priority SCC with an inter-

rupt pending will have a high IEI input; this is the interrupt being acknowledged, and that

source’s internal IUS bit will be set to ‘1’.

When servicing of the SCC has completed, the Reset Highest IUS Command in WR0

must be issued to unlock the daisy chain, reset the IUS bit, and enable lower-priority in-

terrupt requests.

3.5.2

Interrupt Without Acknowledge

In this mode,

INTACK does not have to be generated, and the INTACK input pin must be

tied High. This allows a simpler hardware design that does not have to meet the Interrupt

Acknowledge timing (AC timing parameter #38,TdlAi(RD)). Soon after the SCC’s

INT pin

goes active, an external interrupt controller will jump to the interrupt routine. In the inter-

rupt routine, the code must read RR2 from Channel B to read the vector including status.

When the vector is read from Channel B, it always includes the status regardless of the

VIS bit in WR9 (D0). The status given will decode the highest priority interrupt pending at

the time RR2 is read. Note that the vector is not latched in RR2 so that the next read of

RR2 could produce a different vector if another interrupt occurs; however, accessing RR2

disables it from change during the read operation to prevent an error if a higher interrupt

occurs exactly during the read operation.

Once RR2 is read, the interrupt routine must decode the interrupt pending, and clear the

condition. For example, writing a character to the Transmit Buffer will clear the Transmit

Buffer Empty IP. Removing the interrupt condition clears the IP bit and deactivates

INT, but only if there are no other IP bits set. When the interrupt IP is cleared, RR2

can be read again. This allows the interrupt routine to clear all IPs with one interrupt re-

quest to the processor.

3.5.3

Interrupt With Acknowledge With Vector

In this mode of operation, the processor must respond to the activation of

INT by activat-

ing

INTACK. After enough time has elapsed to allow the daisy chain to settle (AC timing

parameter #38,TdlAi(RD)), the SCC sets the IUS bit for the highest priority IP. If the No

Vector bit in WR9 (D1) is reset to ‘0’, the SCC will then place the interrupt vector on the

data bus during the read strobe.

To speed the interrupt response time, the SCC can also modify 3 bits in the vector to indi-

cate status. If it is programmed to include status information in the vector, this status may

be encoded and placed in either bits 1–3 or in bits 4–6 as programmed by the Status

High/Status Low bit in WR9. To include status, the VIS bit in WR9 (D0) must be set to ‘1’.

The service routine must then clear the interrupting condition. For example, writing a

character to the Transmit Buffer will clear the Transmit Buffer empty IP. After the inter-

rupting condition is cleared, the routine can read RR3 to determine if any other IP bits are

set and clear them. At the end of the interrupt routine, a Reset IUS command must then

be issued via WR0 to unlock the daisy chain and enable lower-priority interrupt requests.

This is the only way, short of a software or hardware reset, that an IUS bit may be reset.

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