5/4/98

AmC0XXCFLKA

11

Table 5.

Word Command Definitions (Note 7)

Notes:

1. Address bit A16 = X = Don’t Care for all address commands except for Program Address (PA) and Sector Address (SA).

2. Bus operations are defined in Table 1.

3. RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.

SA = Address of the sector to be erased. The combination of A17, A18, A19 will uniquely select any sector of a segment.

To select the memory segment:1 and 2 Mbyte: Use CE1, CE2, A20

4 Mbyte:

Use CE1, CE2, A20, A21

0 Mbyte:

Use CE1, CE2, A20–A23.

4. RW = Data read from location RA during read operation. (Word Mode).

PW = Data to be programmed at location PA. Data is latched on the rising edge of WE. (Word Mode).

5. Address for Memory Segment Pair 0 (S0 and S1) only. Address for the higher Memory Segment Pairs (S2, S3 = Pair 1, S4,

S5 = Pair 2, S6, S7 = Pair 3…) is equal to (Addr) + M* (80000H) where M = Memory Segment Pair number.

6. Word = 2 bytes = odd byte and even byte.

7. CE1 = 0 and CE2 = 0.

Table 6.

Memory Sector Address Table

for Memory Segment S0

FLASH MEMORY WRITE/ERASE

OPERATIONS

Details of AMD’s Embedded Write and

Erase Operations

Embedded Erase™ Algorithm

The automatic memory sector or memory segment

erase does not require the device to be entirely prepro-

gramming prior to executing the Embedded Erase

command. Upon executing the Embedded Erase com-

mand sequence, the addressed memory sector or

memory segment will automatically write and verify the

entire memory segment or memory sector for an all

“zero” data pattern. The system is not required to pro-

vide any controls or timing during these operations.

When the memory sector or memory segment is auto-

matically verified to contain an all “zero” pattern, a

self-timed chip erase-and-verify begins. The erase and

verify operations are complete when the data on D7 of

the memory sector or memory segment is “1” (see

“Write Operation Status” section) at which time the

Embedded

Command

Sequence

Bus

Write

Cycles

Req’d

First Bus

Write Cycle

Second Bus

Write Cycle

Third Bus

Write Cycle

Fourth Bus

Read/Write Cycle

Fifth Bus

Write Cycle

Sixth Bus

Write Cycle

Addr*

Data

Addr*

Data

Addr*

Data

Addr*

Data

Addr*

Data

Addr*

Data

Reset/Read

4

AAAAH AAAA 5554H 5555 AAAAH F0F0

RA

RW

Autoselect

4

AAAAH AAAA 5554H 5555 AAAAH 9090 00H/02H

0101/

A4A4

Byte Write

4

AAAAH AAAA 5554H 5555 AAAAH A0A0

PA

PW

Segment Erase

6

AAAAH AAAA 5554H 5555 AAAAH 8080

AAAAH

AAAA

5554H 5555 AAAAH 1010

Sector Erase

6

AAAAH AAAA 5554H 5555 AAAAH 8080

AAAAH

AAAA

5554H 5555

SA

3030

Sector Erase Suspend

Erase can be suspended during sector erase with Addr (don’t care), Data (B0H)

Sector Erase Resume

Erase can be resumed after suspend with Addr (don’t care), Data (30H)

Sector

A19

A18

A17

Address Range

0

0

0

0

00000h-0FFFFh

1

0

0

1

10000h-1FFFFh

2

0

1

0

20000h-2FFFFh

3

0

1

1

30000h-3FFFFh

4

1

0

0

40000h-4FFFFh

5

1

0

1

50000h-5FFFFh

6

1

1

0

60000h-6FFFFh

7

1

1

1

70000h-7FFFFh

Note: A0 is not mapped internally.