AMC004CFLKA datasheet(14/42 Pages) AMD

14 / 42 page

AmC0XXCFLKA

5/4/98

completion of the Embedded Program algorithm an at-

tempt to read the device will produce valid data on D7.

The Data Polling feature is valid after the rising edge of

the fourth WE pulse of the four write pulse sequence.

While the Embedded Erase algorithm is in operation,

D7 will read “0” until the erase operation is completed.

Upon completion of the erase operation, the data on D7

will read “1”.

The Data Polling feature is only active during the Em-

bedded Programming or Erase algorithms. Please note

that the AmC0XXCFLKA data pin (D7) may change

asynchronously while Output Enable (OE) is asserted

low. This means that the device is driving status infor-

mation on D7 at one instant of time and then the byte’s

valid data at the next instant of time. Depending on

when the system samples the D7 output, it may read ei-

ther the status or valid data. Even if the device has

completed the Embedded operation and D7 has a valid

data, the data outputs on D0–D6 may be still invalid

since the switching time for data bits (D0–D7) will not

be the same. This happens since the internal delay

paths for data bits (D0–D7) within the device are differ-

ent. The valid data will be provided only after a certain

time delay (<tOE). Please refer to Figure 4a for detailed

timing diagrams.

See Figures 3 and 5 for the Data Polling timing

specifications and diagrams.

Toggle Bit—D6 (D14 on Odd Byte)

The Flash Memory PC Card also features a “Toggle Bit”

as a method to indicate to the host system that the Em-

bedded algorithms are either in progress or have been

completed.

While the Embedded Program or Erase algorithm is in

progress, successive attempts to read data from the

device will result in D6 toggling between one and zero.

Once the Embedded Program or Erase algorithm is

completed, D6 will stop toggling and valid data on

D0–D7 will be read on the next successive read at-

tempt. The Toggle bit is also used for entering Erase

Suspend mode. Please refer to the section entitled

“Sector Erase Suspend.”

Please note that even if the device completes the Em-

bedded algorithm operation and D6 stops toggling,

data bits D0–D7 (including D6) may not be valid during

the current bus cycle. This may happen since the inter-

nal circuitry may be switching from status mode to the

Read mode. There is a time delay associated with this

mode switching. Since this time delay is always less

than tOE (OE access time), the next successive read at-

tempt (OE going low) will provide the valid data on D0-

D7. Also note that once the D6 bit has stopped toggling

and the output enable OE is held low thereafter (with-

out toggling) the data bits (D0–D7) will be valid after

tOEtime delay.

See Figures 4 and 6 for the Data Polling diagram and

timing specifications.

18723C-3

Figure 2.

Embedded Programming Algorithm in Byte-Wide Mode

Write Embedded Write Command

Sequence per Table 3 or 4

Verify Byte

Yes

Data Poll Device

Yes

Increment Address

Start

Completed

Last

Address

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