W25Q80BWSVIP datasheet(2/74 Pages) WINBOND

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W25Q80BW

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Table of Contents

GENERAL DESCRIPTIONS............................................................................................................. 5

FEATURES....................................................................................................................................... 5

PACKAGE TYPES............................................................................................................................ 6

3.1

Pin Configuration SOIC / VSOP 150 / 208-mil ..................................................................... 6

3.2

PAD Configuration WSON 6x5-mm ..................................................................................... 6

3.3

Pin Description SOIC / VSOP 150/208-mil, WSON 6x5-mm ............................................... 6

3.4

Ball Configuration WLBGA ................................................................................................... 7

3.5

Ball Description WLBGA ...................................................................................................... 7

PIN DESCRIPTIONS........................................................................................................................ 8

4.1

Chip Select (/CS).................................................................................................................. 8

4.2

Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................... 8

4.3

Write Protect (/WP)............................................................................................................... 8

4.4

HOLD (/HOLD) ..................................................................................................................... 8

4.5

Serial Clock (CLK) ................................................................................................................ 8

BLOCK DIAGRAM ............................................................................................................................ 9

FUNCTIONAL DESCRIPTION ....................................................................................................... 10

6.1

SPI OPERATIONS ............................................................................................................. 10

6.1.1

Standard SPI Instructions .....................................................................................................10

6.1.2

Dual SPI Instructions ............................................................................................................10

6.1.3

Quad SPI Instructions ...........................................................................................................10

6.1.4

Hold Function........................................................................................................................10

6.2

WRITE PROTECTION ....................................................................................................... 11

6.2.1

Write Protect Features ..........................................................................................................11

STATUS REGISTERS AND INSTRUCTIONS ............................................................................... 12

7.1

STATUS REGISTERs ........................................................................................................ 12

7.1.1

BUSY Status (BUSY)............................................................................................................12

7.1.2

Write Enable Latch Status (WEL) .........................................................................................12

7.1.3

Block Protect Bits (BP2, BP1, BP0) ......................................................................................12

7.1.4

Top/Bottom Block Protect (TB) .............................................................................................12

7.1.5

Sector/Block Protect (SEC)...................................................................................................12

7.1.6

Complement Protect (CMP)..................................................................................................13

7.1.7

Status Register Protect (SRP1, SRP0) .................................................................................13

7.1.8

Erase/Program Suspend Status (SUS).................................................................................13

7.1.9

Security Register Lock Bits (LB3, LB2, LB1, LB0) ................................................................13

7.1.10

Quad Enable (QE) ..............................................................................................................14

7.1.11

Status Register Memory Protection (CMP = 0) ...................................................................15

7.1.12

Status Register Memory Protection (CMP = 1) ...................................................................16

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