PM6652 datasheet(27/53 Pages) STMICROELECTRONICS

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PM6652

Device description

Doc ID 16867 Rev 5

27/53

8.1.1

Constant on-time PWM architecture

Figure 24 shows the simplified block diagram of a constant on-time controller. A minimum

off-time constraint (250 ns typ.) is introduced to allow inductor valley current sensing on the

synchronous switch. A minimum on-time (70 ns) is also introduced to assure the startup

switching sequence.

The PM6652 has a one-shot generator that turns on the high-side MOSFET when the

following conditions are satisfied simultaneously:

●

The PWM comparator is high

●

The synchronous rectifier current is below the current limit threshold

●

The minimum off-time has timed out.

Once the on-time has timed out, the high-side switch is turned off, while the synchronous

switch is turned on, according to the anti-cross conduction circuitry management.

When the negative input voltage at the PWM comparator reaches the valley limit

(determined by the output voltage), the low-side MOSFET is turned off according to the anti-

cross conduction logic once again, and a new cycle begins.

8.1.2

Output ripple compensation

In a classic constant on-time control, the system regulates the valley value of the output

voltage and not the average value. In this condition, the half of the output voltage ripple is

the equivalent DC static error.

To compensate this error, an integrator network has been introduced in the control loop, by

connecting the CSNS pin to the COMP pin through a capacitor CINT as shown in Figure 25.

The ripple is generated by the output capacitor ESR and by the voltage drop on the sense

resistor RSENSE (inductor’s DCR or dedicated sense resistor). Assuming that ROUT is the

cumulative output capacitors’ ESR, COUT is the cumulative output capacitance and GM is an

internal parameter (Gm = 50 µs typ.), the loop stability requires that the CINT value is:

Equation 5

The integrator amplifier generates a current, proportional to the DC input error, which sets

the output voltage in order to compensate the total static error. In this way the DC output

voltage value is independent of the output ripple, ensuring a very good line and load

regulation.

In addition, CINT provides an AC path for the RSENSE voltage ripple. In steady-state

condition, the voltage at COMP pin is the sum of the output voltage and the output ripple.

OUT

INT

⋅

≥

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