ST8024L

Electrical characteristics

Doc ID 17709 Rev 5

15/35

Table 15.

Clock output to card reader (pin CLK)

Symbol

Test conditions

Min.

Typ.

Max.

Unit

Output voltage in inactive

mode

0

-

0.3

V

No load

0

-

0.1

CLK inactive mode;

pin grounded

0-

–1

mA

Low level output voltage

0

-

0.3

V

-

High level output voltage

V

0

-

0.4

Rise and fall time

(2)

-16

ns

δ

(2)

45

-

55

%

Slew rate

0.2

-

V/ns

1.

2.

Table 16.

Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/3V and PORADJ/1.8V)

Symbol

Test conditions

Min.

Typ.

Max.

Unit

Low level input voltage

–0.3

V

High level input voltage

V

High level input leakage

current

1µA

pins with internal 11 k

Ω pull-

down resistor

800

µA

Low level input leakage

current

-1

µA

internal 11 k

Ω pull-up resistor

-800

µA

Internal pull-down resistor to

GND

Pull-down resistor to GND (1.8V

and CLKDIV2 pins)

911

13

k

Ω

Internal pull-up resistor to

(CLKDIV1 pin)

911

13

k

Ω

1.

Pin CMDVCC is active low; pin RSTIN is active high; for CLKDIV1 and CLKDIV2 functions (see Table 21).