AM186ES-25KCSLASHW datasheet(28/102 Pages) AMD

28 / 102 page

Am186/188ES and Am186/188ESLV Microcontrollers

PRELIMIN ARY

pin is asynchronous to CLKOUTA and is active High.

To guarantee the number of wait states inserted,

ARDY or SRDY must be synchronized to CLKOUTA. If

the falling edge of ARDY is not synchronized to

CLKOUTA as specified, an additional clock period can

be added.

T o alway s a s s e r t the r eady con d iti on to the

microcontroller, tie ARDY High. If the system does not

use ARDY, tie the pin Low to yield control to SRDY.

BHE/ADEN

(Am186ES Microcontroller Only)

Bus High Enable (three-state, output,

synchronous)

Address Enable (input, internal pullup)

BHE—During a memory access, this pin and the least-

significant address bit (AD0 or A0) indicate to the

system which bytes of the data bus (upper, lower, or

both) participate in a bus cycle. The BHE/ADEN and

AD0 pins are encoded as shown in Table 1.

Table 1.

Data Byte Encoding

BHE is asserted during t1 and remains asserted

through t3 and tW. BHE does not need to be latched.

BHE floats during bus hold and reset.

On the Am186ES microcontroller, WLB and WHB

implement the functionality of BHE and AD0 for high

and low byte-write enables.

BHE/ADEN also signals DRAM refresh cycles when

using the multiplexed address and data (AD) bus. A

refresh cycle is indicated when both BHE/ADEN and

AD0 are High. During refresh cycles, the A bus and the

AD bus are not guaranteed to provide the same

address during the address phase of the AD bus cycle.

For this reason, the A0 signal cannot be used in place

of the AD0 signal to determine refresh cycles. PSRAM

refreshes also provide an additional RFSH signal (see

the MCS3/RFSH pin description on page 31).

ADEN—If BHE/ADEN is held High or left floating

during power-on reset, the address portion of the AD

bus (AD15–AD0 for the 186 or AO15–AO8 and AD7–

AD0 for the 188) is enabled or disabled during LCS and

UCS bus cycles based on the DA bit in the LMCS and

UMCS registers. In this case, the memory address is

accessed on the A19–A0 pins. There is a weak internal

pullup resistor on BHE/ADEN so no external pullup is

required. This mode of operation reduces power

consumption.

If BHE/ADEN is held Low on power-on reset, the AD

bus drives both addresses and data, regardless of the

DA bit setting. The pin is sampled on the rising edge of

RE S . ( S 6 a nd UZ I also assum e t heir nor ma l

functionality in this instance. See Table 2 on page 34.)

Note: On the Am188ES microcontroller, AO15–AO8

are driven during the

t2–t4 bus cycle, regardless of the

setting of the DA bit in the UMCS and LMCS registers.

CLKOUTA

Clock Output A (output, synchronous)

This pin supplies the internal clock to the system.

Depending on the value of the system configuration

PLL frequency, the power-save frequency, or is three-

stated. CLKOUTA remains active during reset and bus

hold conditions.

All AC timing sp ecs that use a clock relate to

CLKOUTA.

CLKOUTB

Clock Output B (output, synchronous)

This pin supplies an additional clock with a delayed

output compared to CLKOUTA. Depending upon the

value of the system configuration register (SYSCON),

CLKOUTB operates at either the PLL frequency, the

power-save frequency, or is three-stated. CLKOUTB

remains active during reset and bus hold conditions.

CLKOUTB is not used for AC timing specs.

CTS0/ENRX0/PIO21

Clear-to-Send 0 (input, asynchronous)

Enable-Receiver-Request 0 (input, asynchronous)

CTS0—This pin provides the Clear to Send signal for

asynchronous serial port 0 when the ENRX0 bit in the

AUXCON register is 0 and hardware flow control is

enabled for the port (FC bit in the serial port 0 control

r egister is s e t) . T he C T S 0 si g nal gat es the

transmission of data from the associated serial port

transmit register. When CTS0 is asserted, the

transmitter begins transmission of a frame of data, if

any is available. If CTS0 is deasserted, the transmitter

holds the data in the serial port transmit register. The

value of CTS0 is checked only at the beginning of the

transmission of the frame.

ENRX0—This pin provides the Enable Receiver

Request for asynchronous serial port 0 when the

ENRX0 bit in the AUXCON register is 1 and hardware

flow control is enabled for the port (FC bit in the serial

port 0 control register is set). The ENRX0 signal

enables the receiver for the associated serial port.

BHE

AD0

Type of Bus Cycle

Word Transfer

High Byte Transfer (Bits 15–8)

Low Byte Transfer (Bits 7–0)

Refresh

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